NXP Semiconductors MKW01Z128, Reference Manual, Page: 469 / 884

20.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The MCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus error. Read accesses may be performed in both supervisor
and user mode.
MCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h 20.3.1/338
4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W See section 20.3.2/340
4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 20.3.3/341
4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W See section 20.3.4/341
4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h 20.3.5/343
4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 20.3.6/344
4006_4006 MCG Status Register (MCG_S) 8 R 10h 20.3.7/345
4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 02h 20.3.8/347
4006_400A
MCG Auto Trim Compare Value High Register
(MCG_ATCVH)
8 R/W 00h 20.3.9/348
4006_400B
MCG Auto Trim Compare Value Low Register
(MCG_ATCVL)
8 R/W 00h 20.3.10/348
4006_400C MCG Control 7 Register (MCG_C7) 8 R/W 00h 20.3.11/349
4006_400D MCG Control 8 Register (MCG_C8) 8 R/W 80h 20.3.12/349
4006_400F MCG Control 10 Register (MCG_C10) 8 R/W 00h 20.3.13/350
4006_4011 MCG Control 12 Register (MCG_C12) 8 R/W 00h 20.3.14/350
4006_4012 MCG Status 2 Register (MCG_S2) 8 R/W 00h 20.3.14/351
4006_4013 MCG Test 3 Register (MCG_T3) 8 R/W 00h 20.3.14/351
20.3.1 MCG Control 1 Register (MCG_C1)
Address: 4006_4000h base + 0h offset = 4006_4000h
Bit 7 6 5 4 3 2 1 0
Read
CLKS FRDIV IREFS IRCLKEN IREFSTEN
Write
Reset 0 0 0 0 0 1 0 0
Memory Map/Register Definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
338 Freescale Semiconductor, Inc.