NXP Semiconductors MKW01Z128, Reference Manual

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DMA_DSR_BCRn field descriptions (continued)
Field Description
Set when all DMA controller transactions complete as determined by transfer count, or based on error
conditions. When BCR reaches 0, DONE is set when the final transfer completes successfully. DONE can
also be used to abort a transfer by resetting the status bits. When a transfer completes, software must
clear DONE before reprogramming the DMA.
0 DMA transfer is not yet complete. Writing a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an
interrupt service routine to clear the DMA interrupt and error bits.
BCR BCR
This field contains the number of bytes yet to be transferred for a given block.
Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with a
value in this range, bits 23-20 of BCR read back as 0000b. A write to BCR of a value
greater than 0F_FFFFh causes a configuration error when the channel starts to execute.
After being written with a value in this range, bits 23-20 of BCR read back as 0001b.
19.3.4 DMA Control Register (DMA_DCRn)
Address: 4000_8000h base + 10Ch (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINT ERQ CS AA
0
Reserved EADREQ
SINC SSIZE DINC DSIZE
0
W
START
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SMOD DMOD
D_REQ
0
LINKCC LCH1 LCH2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_DCRn field descriptions
Field Description
31
EINT
Enable Interrupt on Completion of Transfer
Table continues on the next page...
Chapter 19 DMA Controller Module
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 325