NXP Semiconductors MKW01Z128, Reference Manual

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_DSR_BCRn field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
CE
Configuration Error
Any of the following conditions causes a configuration error:
• BCR, SAR, or DAR does not match the requested transfer size.
• A value greater than 0F_FFFFh is written to BCR.
• Bits 31-20 of SAR or DAR are written with a value other than one of the allowed values. See
SAR
and DAR .
• SSIZE or DSIZE is set to an unsupported value.
• BCR equals 0 when the DMA receives a start condition.
CE is cleared at hardware reset or by writing a 1 to DONE.
0 No configuration error exists.
1 A configuration error has occurred.
29
BES
Bus Error on Source
BES is cleared at hardware reset or by writing a 1 to DONE.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
28
BED
Bus Error on Destination
BED is cleared at hardware reset or by writing a 1 to DONE.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
REQ
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
25
BSY
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
24
DONE
Transactions Done
Table continues on the next page...
Memory Map/Register Definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
324 Freescale Semiconductor, Inc.