NXP Semiconductors MKW01Z128, Reference Manual, Page: 33 / 884

Signal Multiplexing and Signal Descriptions
MKW01xxRM Reference Manual, Rev. 3, 04/2016
3-2 Freescale Semiconductor, Inc.
• Port A and port D are each assigned one interrupt. For DMA requests, port A and port D each have
a dedicated input to the DMA multiplex.
• Port A is assigned a dedicated interrupt and port C and port D share an interrupt. For DMA
requests, port A, port C, and port D each have a dedicated input to the DMA multiplex.
The reset state and read/write characteristics of the bit fields within the PORTx_PCRn registers are
summarized in the table below.
3.2.2 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM
module. These bits are cleared after any reset, which disables the clock to the corresponding module to
conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to
enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to
the clock distribution chapter.
3.2.3 Signal multiplexing contraints
A given peripheral function must be assigned to a maximum of one package pin. Do not program the same
function to more than one pin.
Table 3-2. Reset State of PORTx_PCRn Register Bit Fields
This field of
PORTx_PC Rn
Generally
resets to
Except for Resets to Configurability
PS 1 PTA0 0 Yes - All GPIO are configurable
PE 0 PTA0 and PTA2 1 Yes - All GPIO are configurable
DSE 0 No exceptions — 4 pins are configurable for High Drive
(PTB0, PTB1, PTD6, PTD7). All others are
fixed for Normal Drive and the associated
DSE bit is read only.
SRE 1 PTA3, PTA4, PTB17,
PTC3, PTC4, PTC5,
PTC6, PTC7, PTD4,
PTD5, PTD6 PTD7 0 Yes - All GPIO are configurable
MUX 000 PTA0, PTA3, PTA4 111 Yes - All GPIO are configurable
PFE 0 PTA 20, all other PFE
are cleared on reset.
1
1
The RESET pin has the passive analog filter fixed enabled when functioning as the RESET pin (FOPT[RESET_PIN_CFG]
= 1) and fixed disabled when configured for its alternate function: PTA20 (FOPT[RESET_PIN_CFG] = 0).
The GPIO shared with NMI_b pin is
configurable. All other GPIO is fixed and
read only.
IRQC 000 No exceptions - all are
cleared on reset. — Only implemented for ports that support
interrupt and DMA functionality.
ISF 0 No exceptions - all are
cleared on reset. — Only implemented for ports that support
interrupt and DMA functionality.