NXP Semiconductors MKW01Z128, Reference Manual

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7.5.2 Global Pin Control Low Register (PORTx_GPCLR)
Only 32-bit writes are supported to this register.
Address: Base a 80h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
GPWE GPWD
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_GPCLR field descriptions
Field Description
31–16
GPWE
Global Pin Write Enable
Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
7.5.3 Global Pin Control High Register (PORTx_GPCHR)
Only 32-bit writes are supported to this register.
Address: Base a 84h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
GPWE GPWD
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_GPCHR field descriptions
Field Description
31–16
GPWE
Global Pin Write Enable
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
144 Freescale Semiconductor, Inc.