NXP Semiconductors MKW01Z128, Reference Manual

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The MCU uses the bits of FTFA_FOPT to configure the device at reset as shown in the
following table.
Table 4-2. Flash Option Register (FTFA_FOPT) bit definitions
Bit
Num
Field Value Definition
7-6 Reserved Reserved for future expansion.
5 FAST_INIT Selects initialization speed on POR, VLLSx, and any system reset .
0
Slower initialization: The flash initialization will be slower with the benefit of
reduced average current during this time. The duration of the recovery will be
controlled by the clock divider selection determined by the LPBOOT setting.
1 Fast Initialization: The flash has faster recoveries at the expense of higher current
during these times.
3 RESET_PIN_CFG Enables/disables control for the RESET pin.
0
RESET_b pin is disabled following a POR and cannot be enabled as reset
function. When this option is selected, there could be a short period of contention
during a POR ramp where the device drives the pinout low prior to establishing the
setting of this option and releasing the reset function on the pin.
This bit is preserved through system resets and low-power modes. When
RESET_b pin function is disabled, it cannot be used as a source for low-power
mode wake-up.
NOTE: When the reset pin has been disabled and security has been enabled by
means of the FSEC register, a mass erase can be performed only by
setting both the Mass Erase and System Reset Request fields in the
MDM-AP register.
1 RESET_b pin is dedicated. The port is configured with pullup enabled, open drain,
passive filter enabled.
2 NMI_DIS Enables/disables control for the NMI function.
0
NMI interrupts are always blocked. The associated pin continues to default to
NMI_b pin controls with internal pullup enabled. When NMI_b pin function is
disabled, it cannot be used as a source for low-power mode wake-up.
1 NMI_b pin/interrupts reset default to enabled.
1 Reserved Reserved for future expansion.
4,0 LPBOOT Controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register. Larger divide value
selections produce lower average power consumption during POR, VLLSx recoveries and
reset sequencing and after reset exit. The recovery times are also extended if the
FAST_INIT option is not selected.
00
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
10 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Chapter 4 Reset and Boot
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 111