3.5.1 Clock divider values after reset
Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two
bits in the flash memory's FTFA_FOPT register control the reset value of the core clock,
system clock, bus clock, and flash clock dividers as shown in this table.
FTFA_FOPT [4,0]
Core/system clock
Bus/Flash clock
Description
00
0x7 (divide by 8)
0x1 (divide by 2)
Low power boot
01
0x3 (divide by 4)
0x1 (divide by 2)
Low power boot
10
0x1 (divide by 2)
0x1 (divide by 2)
Low power boot
11
0x0 (divide by 1)
0x1 (divide by 2)
Fast clock boot
This gives the user flexibility in selecting between a lower frequency, low-power boot
option and higher frequency, higher power during and after reset.
The flash erased state defaults to fast clocking mode, since these bits reside in flash,
which is logic 1 in the flash erased state. To enable a lower power boot option, program
the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control
bits is cleared, the system is in a slower clock configuration. Upon any system reset, the
clock dividers return to this configurable reset state.
3.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. These dividers must be
programmed prior to entering VLPR mode to guarantee operation. Maximum frequency
limitations for VLPR mode is as follows :
• the core/system clocks are less than or equal to 4 MHz, and
• the bus and flash clocks are less than or equal to 1 MHz
NOTE
When the MCG is in BLPI and clocking is derived from the
Fast IRC, the clock divider controls (MCG_SC[FCRDIV],
SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4])
must be programmed such that the resulting flash clock nominal
frequency is 800 kHz or less. In this case, one example of
correct configuration is MCG_SC[FCRDIV] = 000b,
SIM_CLKDIV1[OUTDIV1] = 0000b, and
SIM_CLKDIV1[OUTDIV4] = 100b, resulting in a divide-by-5
setting.
Internal clocking requirements
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
96
Freescale Semiconductor, Inc.
Summary of Contents for MKW01Z128
Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...
Page 11: ...MKW01xxRM Reference Manual Rev 3 04 2016 xii Freescale Semiconductor Inc...
Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...
Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...