NXP Semiconductors MKW01Z128, Reference Manual

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Clock name Description
Core clock MCGOUTCLK divided by OUTDIV1
Clocks the ARM Cortex-M0+ core.
Platform clock MCGOUTCLK divided by OUTDIV1
Clocks the crossbar switch and NVIC.
System clock MCGOUTCLK divided by OUTDIV1
Clocks the bus masters directly.
Bus clock System clock divided by OUTDIV4.
Clocks the bus slaves and peripherals.
Flash clock Flash memory clock
On this device, it is the same as Bus clock.
MCGIRCLK MCG output of the slow or fast internal reference clock
MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or
MCG's external reference clock that sources the core,
system, bus, and flash clock.
MCGFLLCLK MCG output of the FLL
MCGFLLCLK or MCGPLLCLK may clock some
modules. In addition, this clock is used for UART0 and
TPM modules.
MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may
clock some modules. In addition, this clock is used for
UART0 and TPM modules.
OSCCLK System oscillator output of the internal oscillator or sourced
directly from EXTAL. Used as MCG external reference clock.
OSCERCLK System oscillator output sourced from OSCCLK that may
clock some on-chip modules
OSC32KCLK System oscillator 32 kHz output
ERCLK32K Clock source for some modules that is chosen as
OSC32KCLK or RTC_CLKIN
LPO PMC 1 kHz output
3.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
Table 3-1. Clock summary
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
MCGOUTCLK Up to 100 MHz Up to 4 MHz MCG In all stop modes
except for partial stop
modes and during PLL
locking when
Table continues on the next page...
Chapter 3 Clock Distribution
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 93