Table 39-7. SPI Master (CPHA=1) Configuration (continued)
Register
Value
Comments
Set TIMCMP[7:0] = (baud rate divider /
2) - 1.
TIMCFGn
0x0100_2222
Configure start bit, stop bit, enable on
trigger high and disable on compare,
initial clock state is logic 0. Set PINPOL
to invert the output shift clock. Set
TIMDIS=3 to keep slave select asserted
for as long as there is data in the
transmit buffer.
TIMCTLn
0x01C3_0201
Configure dual 8-bit counter using Pin 2
output (shift clock), with Shifter 0 flag as
the inverted trigger.
TIMCMP(n+1)
0x0000_FFFF
Never compare.
TIMCFG(n+1)
0x0000_1100
Enable when Timer 0 is enabled and
disable when Timer 0 is disabled.
TIMCTL(n+1)
0x0003_0383
Configure 16-bit counter (never
compare) using inverted Pin 3 output (as
slave select).
SHIFTBUFn
Data to transmit
Transmit data can be written to
SHIFTBUF, use the Shifter Status Flag
to indicate when data can be written
using interrupt or DMA request. Can
support MSB first transfer by writing to
SHIFTBUFBBS register instead.
SHIFTBUF(n+1)
Data to receive
Received data can be read from
SHIFTBUFBYS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support MSB first transfer by reading
from SHIFTBUFBIS register instead.
39.5.4 SPI Slave
SPI slave mode can be supported using one Timer, two Shifters and four Pins. Either
CPHA=0 or CPHA=1 can be supported and transfers can be supported using the DMA
controller. For CPHA=1, the select can remain asserted for multiple transfers and the
timer status flag can be used to indicate the end of the transfer.
The transmit data must be written to the transmit buffer register before the external slave
select asserts, otherwise the shifter error flag will be set.
Due to synchronization delays, the output valid time for the serial output data is 2.5
FlexIO clock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock
frequency.
Chapter 39 FlexIO
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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