NXP Semiconductors MKL27Z128VFM4, Reference Manual

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Table 5-1. Clock summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
LPUART1 clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGPCLK,
OSCERCLK
SIM_SOPT2[LPUART1
SRC]=00 selected clock
source disabled
FlexIO clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGPCLK,
OSCERCLK
SIM_SOPT2[FLEXIOS
RC]=00 selected clock
source disabled
USB FS clock 48 MHz N/A MCGPCLK,
USB_CLKIN
USB FS is disabled
I2S master clock Up to 25 MHz Up to 16 MHz System clock,
OSCERCLK,
MCGIRCLK ,
MCGPCLK, I
2
S is disabled
1. If in LIRC mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 1Mhz if executing from flash.
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM_CLKDIV1 register. The following
requirements must be met when configuring the clocks for this device:
• The core, platform, and system clock are programmable from a divide-by-1 through
divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
• The frequency of bus clock and flash clock is divided by the system clock and is
programmable from a divide-by-1 through divide-by-8 setting. The bus clock and
flash clock must be programmed to 24 MHz or slower.
• MCGPCLK is used for peripheral which is fixed to 48 MHz.
• MCGIRCLK is also one of peripheral clock sources which is from IRC8M and can
be divided down by a divider.
The following is a common clock configuration for this device:
Clock Max. Frequency
Core clock 48 MHz
Platform clock 48 MHz
System clock 48 MHz
Bus clock 24 MHz
Flash clock 24 MHz
Table continues on the next page...
Chapter 5 Clock Distribution
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc. 69