M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
S
T
O
P
S
T
A
R
T
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
MODULE
ASYNCH
Figure 37-2. LPUART receiver block diagram
37.3 Register definition
The LPUART includes registers to control baud rate, select LPUART options, report
LPUART status, and for transmit/receive data. Access to an address outside the valid
memory map will generate a bus error.
LPUART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_4000 LPUART Baud Rate Register (LPUART0_BAUD)
32
R/W
0F00_0004h
4005_4004 LPUART Status Register (LPUART0_STAT)
32
R/W
00C0_0000h
4005_4008 LPUART Control Register (LPUART0_CTRL)
32
R/W
0000_0000h
4005_400C LPUART Data Register (LPUART0_DATA)
32
R/W
0000_1000h
4005_4010 LPUART Match Address Register (LPUART0_MATCH)
32
R/W
0000_0000h
4005_5000 LPUART Baud Rate Register (LPUART1_BAUD)
32
R/W
0F00_0004h
4005_5004 LPUART Status Register (LPUART1_STAT)
32
R/W
00C0_0000h
4005_5008 LPUART Control Register (LPUART1_CTRL)
32
R/W
0000_0000h
4005_500C LPUART Data Register (LPUART1_DATA)
32
R/W
0000_1000h
4005_5010 LPUART Match Address Register (LPUART1_MATCH)
32
R/W
0000_0000h
Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
651
