In slave mode, user software should write to SPIMODE only once to prevent corrupting a
transmission in progress.
Note
Data can be lost if the data length is not the same for both
master and slave devices.
35.5.7 SPI clock formats
To accommodate a wide variety of synchronous serial peripherals from different
manufacturers, the SPI system has a Clock Polarity (CPOL) bit and a Clock Phase
(CPHA) control bit in the Control Register 1 to select one of four clock formats for data
transfers. C1[CPOL] selectively inserts an inverter in series with the clock. C1[CPHA]
chooses between two different clock phase relationships between the clock and data.
The following figure shows the clock formats when SPIMODE = 0 (8-bit mode) and
CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1
starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the eighth
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits
depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but
only one of these waveforms applies for a specific transfer, depending on the value in
C1[CPOL]. The SAMPLE IN waveform applies to the MOSI input of a slave or the
MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided C2[MODFEN] and
C1[SSOE] = 1). The master SS output goes to active low one-half SPSCK cycle before
the start of the transfer and goes back high at the end of the eighth bit time of the transfer.
The SS IN waveform applies to the slave select input of a slave.
Chapter 35 Serial Peripheral Interface (SPI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
595
