30.2.2 Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
• Ability of timers to generate interrupts
• Maskable interrupts
• Independent timeout periods for each timer
30.3 Signal description
The PIT module has no external pins.
30.4 Memory map/register description
This section provides a detailed description of all registers accessible in the PIT module.
• Reserved registers will read as 0, writes will have no effect.
• See the chip-specific PIT information for the number of PIT channels used in this
MCU.
PIT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_7000 PIT Module Control Register (PIT_MCR)
32
R/W
0000_0002h
4003_70E0 PIT Upper Lifetime Timer Register (PIT_LTMR64H)
32
R
0000_0000h
4003_70E4 PIT Lower Lifetime Timer Register (PIT_LTMR64L)
32
R
0000_0000h
4003_7100 Timer Load Value Register (PIT_LDVAL0)
32
R/W
0000_0000h
4003_7104 Current Timer Value Register (PIT_CVAL0)
32
R
0000_0000h
4003_7108 Timer Control Register (PIT_TCTRL0)
32
R/W
0000_0000h
4003_710C Timer Flag Register (PIT_TFLG0)
32
R/W
0000_0000h
4003_7110 Timer Load Value Register (PIT_LDVAL1)
32
R/W
0000_0000h
4003_7114 Current Timer Value Register (PIT_CVAL1)
32
R
0000_0000h
4003_7118 Timer Control Register (PIT_TCTRL1)
32
R/W
0000_0000h
4003_711C Timer Flag Register (PIT_TFLG1)
32
R/W
0000_0000h
Chapter 30 Periodic Interrupt Timer (PIT)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
489
