29.5.11 Reset Overview
The TPM is reset whenever any chip reset occurs.
When the TPM exits from reset:
• the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] =
0:0);
• the timer overflow interrupt is zero;
• the channels interrupts are zero;
• the channels are in input capture mode;
• the channels outputs are zero;
• the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0).
29.5.12 TPM Interrupts
This section describes TPM interrupts.
29.5.12.1 Timer Overflow Interrupt
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1).
29.5.12.2 Channel (n) Interrupt
The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1).
Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
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Freescale Semiconductor, Inc.
