power modes it may be desirable to disable the VREF regulator to minimize current
consumption. Note however that the accuracy of the output voltage will be reduced (by as
much as several mVs) when the VREF regulator is not used.
NOTE
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.
26.1.4 VREF Signal Descriptions
The following table shows the Voltage Reference signals properties.
Table 26-1. VREF Signal Descriptions
Signal
Description
I/O
VREF_OUT
Internally-generated Voltage Reference output
O
NOTE
When the VREF output buffer is disabled, the status of the
VREF_OUT signal is high-impedence.
Memory Map and Register Definition
VREF memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_4000 VREF Trim Register (VREF_TRM)
8
R/W
4007_4001 VREF Status and Control Register (VREF_SC)
8
R/W
00h
26.2
Chapter 26 Voltage Reference (VREFV1)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
425
