The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave.
17.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• Up to single-clock 32-bit transfer
• Programmable configuration for fixed-priority or round-robin slave port arbitration
(see the chip-specific information).
17.3 Memory Map / Register Definition
This crossbar switch is designed for minimal gate count. It, therefore, has no memory-
mapped configuration registers.
Please see the chip-specific information for information on whether the arbitration
method in the crossbar switch is programmable, and by which module.
17.4 Functional Description
17.4.1 General operation
When a master accesses the crossbar switch, the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the
requesting master simply sees wait states inserted until the targeted slave port can service
the master's request. The latency in servicing the request depends on each master's
priority level and the responding slave's access time.
Memory Map / Register Definition
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
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Freescale Semiconductor, Inc.
