• Two mid-levels: V
LVW3
and V
LVW2
• Lowest: V
LVW1
15.4 I/O retention
When in LLS mode, the I/O pins are held in their input or output state.
Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full
regulation, and releases the logic from state retention mode. The I/O are released
immediately after a wake-up or reset event. In the case of LLS exit via a RESET pin, the
I/O default to their reset state.
When in VLLS modes, the I/O states are held on a wake-up event (with the exception of
wake-up by reset event) until the wake-up has been acknowledged via a write to
REGSC[ACKISO]. In the case of VLLS exit via a RESET pin, the I/O are released and
default to their reset state. In this case, no write to REGSC[ACKISO] is needed.
15.5 Memory map and register descriptions
Details about the PMC registers can be found here.
NOTE
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details. For
more information about the types of reset on this chip, refer to
the Reset section details.
The PMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
PMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_D000
Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
8
R/W
10h
4007_D001
Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
8
R/W
00h
4007_D002 Regulator Status And Control register (PMC_REGSC)
8
R/W
04h
Chapter 15 Power Management Controller (PMC)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
243
