Table 9-4. MDM-AP Status register assignments (continued)
Bit
Name
Description
This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is
held until the debugger has had a chance to recognize that LLS was exited
and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in
MDM AP Control register.
10
VLLSx Modes Exit
This bit indicates an exit from VLLSx mode has occurred. The debugger
will lose communication while the system is in VLLSx (including access to
this register). Once communication is reestablished, this bit indicates that
the system had been in VLLSx. Since the debug modules lose their state
during VLLSx modes, they need to be reconfigured.
This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit
bit is held until the debugger has had a chance to recognize that a VLLS
mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
11 – 15
Reserved for future use
Always read 0.
16
Core Halted
Indicates the core has entered Debug Halt mode
17
Core SLEEPDEEP
Indicates the core has entered a low-power mode
SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.
SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.
18
Core SLEEPING
19 – 31
Reserved for future use
Always read 0.
9.4 Debug resets
The debug system receives the following sources of reset:
• System POR reset
Conversely, the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• SYSRESETREQ field in the NVIC Application Interrupt and Reset control register
• A system reset in the DAP control register which allows the debugger to hold the
core in reset.
9.5 Micro Trace Buffer (MTB)
The Micro Trace Buffer (MTB) provides a simple execution trace capability for the
Cortex-M0+ processor.
Debug resets
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Freescale Semiconductor, Inc.
