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NXP Semiconductors MCF5272 ColdFire User Manual Download Page 70

ColdFire Core

MCF5272 ColdFire

®

 Integrated Microprocessor User’s Manual, Rev. 3

2-2

Freescale Semiconductor

 

Figure 2-1. ColdFire Pipeline

2.1.1.1

Instruction Fetch Pipeline (IFP)

The IFP generates instruction addresses and fetches. Because the fetch and execution pipelines are 
decoupled by a three longword FIFO buffer, the IFP can prefetch instructions before the OEP needs them, 
minimizing stalls.

2.1.1.2

Operand Execution Pipeline (OEP)

The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file feeding an 
arithmetic/logic unit (ALU). For simple register-to-register instructions, the first stage of the OEP 
performs the instruction decode and fetching of the required register operands (OC), while the actual 
instruction execution is performed in the second stage (EX). 

For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the 
following way:

•

The instruction is decoded and the components of the operand address are selected (DS). 

•

The operand address is generated using the execute engine (AG).

•

The memory operand is fetched while any register operand is simultaneously fetched (OC).

•

The instruction is executed (EX).

Instruction 

Instruction

FIFO 

Decode & Select,

Address 

 

Data[31:0]

IAG

IC

IB

DSOC

AGEX

Address [31:0]

Instruction Buffer

Address 

Generation

Fetch Cycle

Generation,

Execute

Operand Fetch

Operand
Execution
Pipeline

Instruction
Fetch
Pipeline

Summary of Contents for MCF5272 ColdFire

Page 1: ...ColdFire Microcontrollers freescale com MCF5272 ColdFire Integrated Microprocessor User s Manual MCF5272UM Rev 3 03 2007...

Page 2: ......

Page 3: ...B Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus...

Page 4: ...B Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus...

Page 5: ...he Block Diagram 4 8 4 4 Cache Control Register CACR 4 12 4 5 Access Control Register Format ACRn 4 14 5 1 Processor Debug Module Interface 5 1 5 2 PSTCLK Timing 5 2 5 3 Example JMP Instruction Output...

Page 6: ...e Base Address Register MBAR 6 4 6 3 System Configuration Register SCR 6 5 6 4 System Protection Register SPR 6 6 6 5 Power Management Register PMR 6 7 6 6 Activate Low Power Register ALPR 6 10 6 7 De...

Page 7: ...0 6 11 1 Ethernet Block Diagram 11 2 11 2 Fast Ethernet Module Block Diagram 11 2 11 3 Ethernet Frame Format 11 4 11 4 Ethernet Address Recognition Flowchart 11 7 11 5 Ethernet Control Register ECR 11...

Page 8: ...2 18 USB Endpoint 0 Interrupt Mask EP0IMR and General Endpoint 0 Interrupt Registers EP0ISR 12 22 12 19 USB Endpoints 1 7 Interrupt Status Registers EPnISR 12 25 12 20 USB Endpoint 1 7 Interrupt Mask...

Page 9: ...Request Registers PDRQR 13 32 13 33 Sync Delay Registers P0SDR P3SDR 13 33 13 34 Clock Select Register PCSR 13 34 13 35 Port 1 Configuration Register P1CR 13 36 13 36 Port 1 Interrupt Configuration R...

Page 10: ...nd Registers UOP1 UOP0 16 18 16 21 UART Block Diagram Showing External and Internal Interface Signals 16 18 16 22 UART RS 232 Interface 16 19 16 23 Clocking Source Diagram 16 20 16 24 Transmitter and...

Page 11: ...11 32 Bit Port Internal Termination 20 16 20 17 Longword Write with Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination 20 17 20 18 Example of a Misaligned Longword Transfer 20 18 2...

Page 12: ...23 19 23 14 MII Serial Management Channel Timing Diagram 23 20 23 15 Timer Timing 23 21 23 16 UART Timing 23 22 23 17 IDL Master Timing 23 23 23 18 IDL Slave Timing 23 25 23 19 GCI Slave Mode Timing 2...

Page 13: ...2 4 Timer Module 1 7 1 2 5 Test Access Port 1 7 1 3 System Design 1 7 1 3 1 System Bus Configuration 1 7 1 4 MCF5272 Specific Features 1 7 1 4 1 Physical Layer Interface Controller PLIC 1 7 1 4 2 Puls...

Page 14: ...Organization of Data in Registers 2 10 2 4 1 Organization of Integer Data Formats in Registers 2 10 2 4 2 Organization of Integer Data Formats in Memory 2 11 2 5 Addressing Mode Summary 2 12 2 6 Inst...

Page 15: ...Overview 4 7 4 5 1 Instruction Cache Physical Organization 4 7 4 5 2 Instruction Cache Operation 4 8 4 5 2 1 Interaction with Other Modules 4 8 4 5 2 2 Cache Coherency and Invalidation 4 8 4 5 2 3 Ca...

Page 16: ...Write A D Register WAREG WDREG 5 23 5 5 3 3 3 Read Memory Location READ 5 24 5 5 3 3 4 Write Memory Location WRITE 5 25 5 5 3 3 5 Dump Memory Block DUMP 5 27 5 5 3 3 6 Fill Memory Block FILL 5 28 5 5...

Page 17: ...Interrupt Controller 7 1 Overview 7 1 7 2 Interrupt Controller Registers 7 2 7 2 1 Interrupt Controller Registers 7 3 7 2 2 Interrupt Control Registers ICR1 ICR4 7 4 7 2 2 1 Interrupt Control Register...

Page 18: ...9 10 SDRAM Interface 9 14 9 10 1 SDRAM Read Accesses 9 15 9 10 2 SDRAM Write Accesses 9 18 9 10 3 SDRAM Refresh Timing 9 20 Chapter 10 DMA Controller 10 1 DMA Data Transfer Types 10 1 10 2 DMA Addres...

Page 19: ...rt Register FRSR 11 20 11 5 11 Transmit FIFO Watermark TFWR 11 21 11 5 12 FIFO Transmit Start Register TFSR 11 22 11 5 13 Receive Control Register RCR 11 23 11 5 14 Maximum Frame Length Register MFLR...

Page 20: ...2 12 3 2 7 USB Device Request Data 1 and 2 Registers DRR1 2 12 13 12 3 2 8 USB Specification Number Register SPECR 12 14 12 3 2 9 USB Endpoint 0 Status Register EP0SR 12 14 12 3 2 10 USB Endpoint 0 IN...

Page 21: ...12 36 12 5 1 Attachment Detection 12 36 12 5 2 PCB Layout Recommendations 12 36 12 5 3 Recommended USB Protection Circuit 12 37 Chapter 13 Physical Layer Interface Controller PLIC 13 1 Introduction 13...

Page 22: ...22 13 5 11 Aperiodic Status Register PASR 13 23 13 5 12 GCI Monitor Channel Receive Registers P0GMR P3GMR 13 24 13 5 13 GCI Monitor Channel Transmit Registers P0GMT P3GMT 13 25 13 5 14 GCI Monitor Ch...

Page 23: ...14 7 14 4 4 Transfer Length 14 8 14 4 5 Data Transfer 14 8 14 5 Programming Model 14 9 14 5 1 QSPI Mode Register QMR 14 9 14 5 2 QSPI Delay Register QDLYR 14 11 14 5 3 QSPI Wrap Register QWR 14 12 14...

Page 24: ...UDUn UDLn 16 14 16 3 12 UART Autobaud Registers UABUn UABLn 16 14 16 3 13 UART Transmitter FIFO Registers UTFn 16 15 16 3 14 UART Receiver FIFO Registers URFn 16 16 16 3 15 UART Fractional Precision...

Page 25: ...egister PDCNT 17 8 17 3 Data Direction Registers 17 10 17 3 1 Port A Data Direction Register PADDR 17 10 17 3 2 Port B Data Direction Register PBDDR 17 10 17 3 3 Port C Data Direction Register PCDDR 1...

Page 26: ...O GPIO Ports 19 24 19 10 UART0 Module Signals and PB 4 0 19 24 19 10 1 Transmit Serial Data Output URT0_TxD PB0 19 24 19 10 2 Receive Serial Data Input URT0_RxD PB1 19 25 19 10 3 Clear to Send URT0_CT...

Page 27: ...SPI Synchronous Serial Data Input QSPI_Din 19 30 19 15 3 QSPI Serial Clock QSPI_CLK BUSW1 19 30 19 15 4 Synchronous Peripheral Chip Select 0 QSPI_CS0 BUSW0 19 30 19 15 5 Synchronous Peripheral Chip Se...

Page 28: ...19 36 19 17 6 Freescale Test Mode Select MTMOD 19 36 19 17 7 Debug Transfer Error Acknowledge TEA 19 36 19 17 8 Processor Status Outputs PST 3 0 19 36 19 17 9 Debug Data DDATA 3 0 19 37 19 17 10 Devic...

Page 29: ...23 Electrical Characteristics 23 1 Maximum Ratings 23 1 23 1 1 Supply Input Voltage and Storage Temperature 23 1 23 1 2 Operating Temperature 23 2 23 1 3 Resistance 23 2 23 2 DC Electrical Specificati...

Page 30: ...s 23 22 23 9 PLIC Module IDL and GCI Interface Timing Specifications 23 23 23 10 General Purpose I O Port AC Timing Specifications 23 28 23 11 USB Interface AC Timing Specifications 23 29 23 12 IEEE 1...

Page 31: ...neral Branch Instruction Execution Times 2 25 2 17 Bcc Instruction Execution Times 2 25 2 18 Exception Vector Assignments 2 26 2 19 Format Field Encoding 2 27 2 20 Fault Status Encodings 2 28 2 21 MCF...

Page 32: ...tions 6 6 6 5 PMR Field Descriptions 6 8 6 6 USB and USART Power Down Modes 6 9 6 7 Exiting Sleep and Stop Modes 6 10 6 8 DIR Field Descriptions 6 11 6 9 WRRR Field Descriptions 6 12 6 10 WIRR Field D...

Page 33: ...y Map 11 10 11 7 ECR Field Descriptions 11 11 11 8 EIR Field Descriptions 11 12 11 9 EIMR Register Field Descriptions 11 13 11 10 IVSR Field Descriptions 11 14 11 11 RDAR Register Field Descriptions 1...

Page 34: ...Descriptions 12 27 12 18 EPnDPR Field Descriptions 12 28 12 19 USB FIFO Access Timing 12 30 12 20 Example FIFO Setup 12 32 13 1 PLIC Module Memory Map 13 13 13 2 P0CR P3CR Field Descriptions 13 19 13...

Page 35: ...escriptions 16 18 16 15 UART Module Signals 16 19 16 16 Transmitter FIFO Status Bits 16 25 16 17 Receiver FIFO Status Bits 16 26 17 1 GPIO Signal Multiplexing 17 1 17 2 GPIO Port Register Memory Map 1...

Page 36: ...ions 23 5 23 7 Processor Bus Input Timing Specifications 23 6 23 8 Processor Bus Output Timing Specifications 23 8 23 9 Debug AC Timing Specification 23 13 23 10 SDRAM Interface Timing Specifications...

Page 37: ...Chip Select Register Memory Map A 3 A 6 GPIO Port Register Memory Map A 3 A 7 QSPI Module Memory Map A 4 A 8 PWM Module Memory Map A 4 A 9 DMA Module Memory Map A 4 A 10 UART0 Module Memory Map A 5 A...

Page 38: ...MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 xxxviii Freescale Semiconductor...

Page 39: ...been linked to the appropriate location Document Revision History Rev No Substantive Change s 2 1 Updated to meet Freescale identity guidelines 3 Formatting layout spelling and grammar corrections Co...

Page 40: ...2 ColdFire Core provides an overview of the microprocessor core of the MCF5272 The chapter describes the organization of the Version 2 V2 ColdFire 5200 processor core and an overview of the program vi...

Page 41: ...nsceiver connection information for both MII and seven wire serial interfaces The chapter concludes with detailed descriptions of operation and the programming model Chapter 12 Universal Serial Bus US...

Page 42: ...teraction Operation of the bus is defined for transfers initiated by the MCF5272 as a bus master The MCF5272 does not support external bus masters Note that Chapter 9 SDRAM Controller describes DRAM c...

Page 43: ...nuals These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual These include the following ColdFi...

Page 44: ...ons for registers are shown in uppercase Specific bits fields or ranges appear in brackets For example RAMBAR BA identifies the base address field in the RAM base address register nibble A 4 bit data...

Page 45: ...MA Direct memory access DSP Digital signal processing EA Effective address EDO Extended data output DRAM FIFO First in first out GPIO General purpose I O I2 C Inter integrated circuit IEEE Institute f...

Page 46: ...t recently used POR Power on reset PQFP Plastic quad flat pack PWM Pulse width modulation QSPI Queued serial peripheral interface RISC Reduced instruction set computing Rx Receive SIM System integrati...

Page 47: ...Dx Source and destination data registers respectively Rc Any control register example VBR is the vector base register Rm MAC registers ACC MAC MASK Rn Any address or data register Rw Destination regis...

Page 48: ...ons Operations Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator x Arithmetic multiplication Arithmetic division Invert operand is logically complemented...

Page 49: ...it displacement Address Calculated effective address pointer Bit Bit selection example Bit 3 of D0 lsb Least significant bit example lsb of D0 LSB Least significant byte LSW Least significant word msb...

Page 50: ...stem Configuration Register SCR No change 0x0006 System Protection Register SPR No change 0x0008 Power Management Register PMR No change 0x000E Activate Low Power Register ALPR No change 0x0010 Device...

Page 51: ...IO Port Register Memory Map MBAR Offset Register Name Old Mnemonic New Mnemonic 0x0080 Port A Control Register PACNT No change 0x0084 Port A Data Direction Register PADDR No change 0x0086 Port A Data...

Page 52: ...PWWD2 Table ix DMA Module Memory Map MBAR Offset Register Name Old Mnemonic New Mnemonic 0x00E0 DMA Mode Register DCMR No change 0x00E6 DMA Interrupt Register DCIR No change 0x00E8 DMA Byte Count Reg...

Page 53: ...P Bit Reset Command Register U1OP0 U0OP0 Table xi UART1 Module Memory Map MBAR Offset Register Name Old Mnemonic New Mnemonic 0x0140 UART1 Mode Register 1 2 U2MR1 U2MR2 U1MR1 U1MR2 0x0144 UART1 Statu...

Page 54: ...TMR0 0x0204 Timer 0 Reference Register TRR1 TRR0 0x0208 Timer 0 Capture Register TCR1 TCAP0 0x020C Timer 0 Counter Register TCN1 TCN0 0x0210 Timer 0 Event Register TER1 TER0 0x0220 Timer 1 Mode Regis...

Page 55: ...B1 Data Receive PLRB13 P3B1RR 0x0310 Port0 B2 Data Receive PLRB20 P0B2RR 0x0314 Port1 B2 Data Receive PLRB21 P1B2RR 0x0318 Port2 B2 Data Receive PLRB22 P2B2RR 0x031C Port3 B2 Data Receive PLRB23 P3B2R...

Page 56: ...MT2 PLGMT3 P2GMT P3GMT 0x0370 GCI Monitor TX Status GCI Monitor TX abort PLGMTS PLGMTA PGMTS PGMTA 0x0374 Port0 3 GCI C I RX PLGCIR0 PLGCIR1 PLGCIR2 PLGCIR3 P0GCIR P1GCIR P2GCIR P3GCIR 0x0378 Port0 3...

Page 57: ...termark X_WMRK TFWR 0x08EC Ethernet Tx FIFO Start Address X_FSTART TFSR 0x0944 Ethernet Rx Control Register R_CNTRL RCR 0x0948 Maximum Frame Length Register MAX_FRM_LEN MFLR 0x0984 Ethernet Tx Control...

Page 58: ...BEPCFG7 EP7CFG 0x104C USB Endpoint 0 Control Register USBEPCTL0 EP0CTL 0x1052 USB Endpoint 1 Control Register USBEPCTL1 EP1CTL 0x1056 USB Endpoint 2 Control Register USBEPCTL2 EP2CTL 0x105A USB Endpoi...

Page 59: ...0AC USB Endpoint 0 Data Register USBEPDAT0 EP0DR 0x10B0 USB Endpoint 1 Data Register USBEPDAT1 EP1DR 0x10B4 USB Endpoint 2 Data Register USBEPDAT2 EP2DR 0x10B8 USB Endpoint 3 Data Register USBEPDAT3 E...

Page 60: ...MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 lx Freescale Semiconductor...

Page 61: ...DSP and fast multiply operations On chip memories 4 Kbyte SRAM on CPU internal bus 16 Kbyte ROM on CPU internal bus 1 Kbyte instruction cache Power management Fully static operation with processor sle...

Page 62: ...er 3 X 32 Decode Select Operand Fetch Address Generation Execute IFP OEP D 31 0 Instruction Address Generation Memory Instruction Bus SDRAM Controller External Bus Interface SYSTEM INTEGRATION MODULE...

Page 63: ...ce bus SDRAM controller supports 16 256 Mbit devices External bus configurable for 16 or 32 bits width for SDRAM Glueless interface to SRAM devices with or without byte strobe inputs Programmable wait...

Page 64: ...ge 3 3 V 0 3 V Operating temperature 0 70 C Operating frequency DC to 66 MHz from external CMOS oscillator Compact ultra low profile 196 ball molded plastic ball grid array package PGBA 1 2 MCF5272 Ar...

Page 65: ...e The external bus interface EBI handles the transfer of information between the internal core and memory peripherals or other processing elements in the external address space 1 2 2 2 Chip Select and...

Page 66: ...ormal operation the external interrupts cause the power management logic to re enable the external clock input The MCF5272 resumes program execution from where it entered stop mode if no interrupt are...

Page 67: ...ction Group The IEEE 1149 1 Standard provides more information 1 3 System Design This section presents issues to consider when designing with the MCF5272 It describes differences between the MCF5272 c...

Page 68: ...converter 1 4 3 Queued Serial Peripheral Interface QSPI The QSPI module provides a serial peripheral interface with queued transfer capability It supports up to 16 stacked transfers at a time making C...

Page 69: ...ress bus supporting 4 Gbytes of linear address space 32 bit data bus 16 user accessible 32 bit wide general purpose registers Supervisor user modes for system protection Vector base register to reloca...

Page 70: ...ons the first stage of the OEP performs the instruction decode and fetching of the required register operands OC while the actual instruction execution is performed in the second stage EX For memory t...

Page 71: ...f digital signal processing DSP operations used in embedded code while supporting the integer multiply instructions in the ColdFire microprocessor family The MAC features a three stage execution pipel...

Page 72: ...point register PBR PC breakpoint mask register PBMR Data operand address breakpoint registers ABHR ABLR Data breakpoint register DBR Data breakpoint mask register DBMR Trigger definition register TDR...

Page 73: ...pointer A7 used during stacking for subroutine calls returns and exception handling The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction...

Page 74: ...tion Code Register CCR The CCR Figure 2 4 occupies SR 7 0 as shown in Figure 2 3 CCR 4 0 are indicator flags based on results generated by arithmetic operations 7 6 5 4 3 2 1 0 Field X N Z V C Reset 0...

Page 75: ...of the final operation involving the product and accumulator 2 2 2 Supervisor Programming Model The MCF5272 supervisor programming model is shown in Figure 2 3 Typically system programmers use the su...

Page 76: ...111 000 R W R W R R W R W R R W R R W R W R W R W R W Figure 2 5 Status Register SR Table 2 3 Status Field Descriptions Bits Name Description 15 T Trace enable When T is set the processor performs a t...

Page 77: ...F5272 ROM contains data for the HDLC module and is not user programmable See Section 4 4 2 1 ROM Base Address Register ROMBAR 2 2 2 6 RAM Base Address Register RAMBAR The RAMBAR register determines th...

Page 78: ...erands When an address register is a source operand either the low order word or the entire longword operand is used depending on the operation size Word length source operands are sign extended to 32...

Page 79: ...rd is located at address N 2 The address N of a word data item corresponds to the address of the high order byte The lower order byte is located at address N 1 This organization is shown in Figure 2 9...

Page 80: ...essing modes from the M68000 family are available on ColdFire microprocessors Table 2 5 summarizes these modes and their categories Table 2 5 ColdFire Effective Addressing Modes Addressing Modes Synta...

Page 81: ...ress register 3 Ay Ax Source and destination address registers respectively Dn Any data register n example D5 is data register 5 Dy Dx Source and destination data registers respectively Rc Any control...

Page 82: ...increment indicator Arithmetic subtraction or predecrement indicator x Arithmetic multiplication Arithmetic division Invert operand is logically complemented Logical AND Logical OR Logical exclusive O...

Page 83: ...Most significant word Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero Table 2 7 User Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation ADD...

Page 84: ...ed operation DIVU ea 1 y Dx Dy ea x W L Dx ea y Dx 16 bit remainder 16 bit quotient Dx ea y Dx 32 bit quotient Unsigned operation EOR Dy ea x L Source destination destination EORI data Dx L Immediate...

Page 85: ...CC ea 1 y MASK Rw MULS ea y Dx W X W L L X L L Source destination destination Signed operation MULU ea y Dx W X W L L X L L Source destination destination Unsigned operation NEG Dx L 0 destination des...

Page 86: ...can be configured to allow user mode execution by setting CSR UHE Table 2 8 Supervisor Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation CPUSHL bc Ax Unsized Invalidate i...

Page 87: ...ns is two cycles The OEP can complete all memory accesses without memory causing any stall conditions Thus timing details in this section assume an infinite zero wait state memory attached to the core...

Page 88: ...SF equals ET with ea d8 An Xi SF The nomenclature xxx wl refers to both forms of absolute addressing xxx w and xxx l Table 2 10 lists execution times for MOVE B W instructions Table 2 10 Move Byte an...

Page 89: ...pth is exposed and execution time is three cycles Table 2 11 Move Long Execution Times Source Destination Rx Ax Ax Ax d16 Ax d8 Ax Xi SF xxx wl Dy 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 0 0 1...

Page 90: ...1 0 0 neg l Dx 1 0 0 negx l Dx 1 0 0 not l Dx 1 0 0 scc Dx 1 0 0 swap Dx 1 0 0 tst b ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst w ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst l...

Page 91: ...x 1 0 0 lea ea Ax 1 0 0 1 0 0 2 0 0 1 0 0 lsl l ea Dx 1 0 0 1 0 0 lsr l ea Dx 1 0 0 1 0 0 mac w Ry Rx 1 0 0 mac l Ry Rx 3 0 0 msac w Ry Rx 1 0 0 msac l Ry Rx 3 0 0 mac w Ry Rx ea Rw 3 1 0 3 1 0 3 1 0...

Page 92: ...0 1 0 0 move w SR Dx 1 0 0 move w ea SR 7 0 0 7 0 0 movec Ry Rc 9 0 1 movem l 1 1 n is the number of registers moved by the MOVEM opcode ea list 1 n n 0 1 n n 0 movem l list ea 1 n 0 n 1 n 0 n nop 3 0...

Page 93: ...itiated It is comprised of the following four major steps 1 The processor makes an internal copy of the SR and then enters supervisor mode by setting SR S and disabling trace mode by clearing SR T The...

Page 94: ...ted as 4 x vector_number When the index value is generated the vector table contents determine the address of the first instruction of the desired handler After the fetch of the first opcode of the ha...

Page 95: ...records any longword misalignment of the stack pointer that may have existed when the exception occurred Fault status field The 4 bit field FS 3 0 at the top of the system stack is defined for access...

Page 96: ...d read the processor immediately aborts the current instruction execution and initiates exception processing In this case any address register changes caused by the auto addressing modes An and An hav...

Page 97: ...lects the just loaded value Because ColdFire processors do not support hardware stacking of multiple exceptions it is the responsibility of the operating system to check for trace mode after processin...

Page 98: ...the processor in supervisor mode by setting SR S and disables tracing by clearing SR T This exception also clears SR M and sets the processor s interrupt priority mask in the SR to the highest level...

Page 99: ...ons including digital audio and servo control Integrated as an execution unit in the processor s OEP the MAC unit implements a three stage arithmetic pipeline optimized for 16 x 16 multiplies Both 16...

Page 100: ...e would be excessive in an embedded environment In striking a middle ground between speed size and functionality the ColdFire MAC unit is optimized for a small set of operations that involve multiplic...

Page 101: ...multiplier array is implemented in a 3 stage pipeline MAC instructions can have an effective issue rate of one clock for word operations three for longword integer operations and four for 32 bit fract...

Page 102: ...hose internal representation is 0x8000 and 0x0x8000_0000 respectively The most positive word is 0x7FFF or 1 2 15 the most positive longword is 0x7FFF_FFFF or 1 2 31 3 2 MAC Instruction Execution Timin...

Page 103: ...e sent simultaneously to the SRAM ROM and cache controllers This approach is required because the controllers are memory mapped devices and the hit miss determination is made concurrently with the rea...

Page 104: ...ocation of the memory block can be set to any 4 Kbyte address boundary within the 4 Gbyte address space The memory is ideal for storing critical code or data structures or for use as the system stack...

Page 105: ...4 Kbyte space defined by BA SRAM can reside on any 4 Kbyte boundary in the 4 Gbyte address space 11 9 Reserved should be cleared 8 WP Write protect Controls read write properties of the SRAM 0 Allows...

Page 106: ...ed to generate line sized burst fetches on 0 modulo 16 addresses so this opcode generally provides the best performance 3 After data is loaded into the SRAM it may be appropriate to load a revised val...

Page 107: ...he 4 Gbyte address space Section 4 1 Interactions Between Local Memory Modules describes priorities when a fetch address hits multiple local memory resources 4 4 2 ROM Programming Model The MCF5272 im...

Page 108: ...odules in a specific address space If an address space is disabled an access to the register in that address space becomes an external bus access and the module resource is not accessed These bits are...

Page 109: ...s in a single cycle The tag array maintains a single valid bit per line entry Accordingly only entire 16 byte lines are loaded into the instruction cache The instruction cache also contains a 16 byte...

Page 110: ...AM module are connected to the ColdFire core s local data bus certain user defined configurations can result in simultaneous instruction fetch processing If the referenced address is mapped into the S...

Page 111: ...ing mask effective attributes ACR1 attributes else effective attributes CACR default attributes Addresses matching an ACR can also be write protected using ACR WP Reset disables the cache and clears a...

Page 112: ...nsure the consistency of cached data execute a CPUSHL instruction or set CACR CINVA to invalidate the entire cache before switching cache modes CPU space register accesses such as MOVEC are treated as...

Page 113: ...t at the time of the next cache miss the line fill buffer contents are written into the cache memory array and the fill buffer data is still most recently used compared to the cache memory array The f...

Page 114: ...lumn indicates whether the corresponding register can be read written or both Attempts to read a write only register cause zeros to be returned Attempts to write to a read only register are ignored 4...

Page 115: ...struction accesses 16 or 32 bits 1 Fill buffer used to store noncacheable accesses The fill buffer is used only for normal TT 0 instruction reads of a noncacheable region Instructions are loaded into...

Page 116: ...e Line Line 31 24 23 16 15 14 13 12 7 6 5 4 3 2 1 0 Field BA BAM EN SM CM BWE WP Reset 0000_0000_0000_0000 R W Write R W by debug module Rc ACR0 0x004 ACR1 0x005 Figure 4 5 Access Control Register For...

Page 117: ...further decouples the write instruction from the signaling of the fault 0 Termination of an operand write cycle on the processor s local bus is delayed until the external bus cycle is completed 1 A wr...

Page 118: ...Local Memory MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 4 16 Freescale Semiconductor...

Page 119: ...gging in the ColdFire processor complex In BDM the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers The external emulator uses a three...

Page 120: ...Serial Output DSO Provides serial output communication for debug module responses DSO is registered internally Breakpoint BKPT Input used to request a manual breakpoint Assertion of BKPT puts the pro...

Page 121: ...both storage elements contain valid data to be dumped to the DDATA port The core stalls until one FIFO entry is available Table 5 2 shows the encoding of these signals Table 5 2 Processor Status Enco...

Page 122: ...TA pins Encodings 0x9 0xB identify the number of bytes displayed 3 The new target address is optionally available on subsequent cycles using the DDATA port The number of bytes of the target address di...

Page 123: ...ming Model In addition to the existing BDM commands that provide access to the processor s registers and the memory subsystem the debug module contains nine registers to support the required functiona...

Page 124: ...er definition register TDR 0x0000_0000 p 5 14 0x08 Program counter breakpoint register PBR p 5 13 0x09 Program counter breakpoint mask register PBMR p 5 13 0x0A 0x0B Reserved 0x0C Address breakpoint h...

Page 125: ...ardware Register BDM Function Breakpoint Function AATR Bus attributes for all memory commands Attributes for address breakpoint ABHR Address for all memory commands Address for address breakpoint DBR...

Page 126: ...modifier Compared with the local bus transfer modifier signals which give supplemental information for each transfer type TT 00 normal mode 000 Explicit cache line push 001 User data access 010 User...

Page 127: ...elds Table 5 7 describes ABHR fields 31 0 Field Address Reset R W Write only ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port usin...

Page 128: ...by a CSR read when either a level 2 breakpoint is triggered or a level 1 breakpoint is triggered and the level 2 breakpoint is disabled 0000 No breakpoints enabled 0001 Waiting for level 1 breakpoint...

Page 129: ...egin Execution of Taken Branch PST 0x5 7 Reserved should be cleared 6 NPL Non mode Determines whether the core operates in pipelined or mode or not 0 Pipelined mode 1 Nonpipelined mode The processor e...

Page 130: ...DMREG and WDMREG commands DBMR is accessible in supervisor mode as debug control register 0x0F using the WDEBUG instruction and via the BDM port using the WDMREG command DRc 4 0 0x0E DBR 0x0F DBMR Fig...

Page 131: ...oint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 5 5 3 3 Command Set Descriptions...

Page 132: ...DR fields 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field TRC EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI Reset 0000_0000_0000_0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field...

Page 133: ...le data byte High order byte of the low order word 23 7 EDUM Upper middle data byte Low order byte of the high order word 22 6 EDUU Upper upper data byte High order byte of the high order word 21 5 DI...

Page 134: ...ending halt condition at the sample time the processor suspends execution and enters the halted state The assertion of BKPT should be considered in the following two special cases After the system res...

Page 135: ...Timing DSCLK and DSI are synchronized inputs DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI DSO is delayed from the DSCLK enabled CLK ri...

Page 136: ...ponse can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock periods S DataMessage 0 xxxxValid data transf...

Page 137: ...word address Steal 5 5 3 3 3 0x1900 byte 0x1940 word 0x1980 lword Writememory location write Write the operand data to the memory location specified by the longword address Steal 5 5 3 3 4 0x1800 byte...

Page 138: ...tension words is defined as address data or operand data 15 10 9 8 7 6 5 4 3 2 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 5 15 BDM Command Format Table 5 18 BDM Field Descripti...

Page 139: ...6 address bits The debug module returns a not ready response unless the received command is decoded as unimplemented which is indicated by the illegal command encoding If this occurs the development s...

Page 140: ...t data 5 5 3 3 Command Set Descriptions The following sections describe the commands summarized in Table 5 17 NOTE The BDM status bit S is 0 for normally completed commands S 1 for illegal commands no...

Page 141: ...d Command Format Command Sequence Figure 5 20 WAREG WDREG Command Sequence Operand Data Longword data is written into the specified address or data register The data is supplied most significant word...

Page 142: ...tion Result Data Word results return 16 bits of data longword results return 32 Bytes are returned in the LSB of a word result the upper byte is undefined 0x0001 S 1 is returned if a bus error occurs...

Page 143: ...space is defined by BAAR TT TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned...

Page 144: ...nd 32 bit operands are sent as 16 and 32 bits respectively Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete A value of 0x0001 wit...

Page 145: ...OTE DUMP does not check for a valid address it is a valid command only when preceded by NOP READ or another DUMP command Otherwise an illegal command response is returned NOP can be used for intercomm...

Page 146: ...size 1 2 or 4 and saved in a temporary register after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated addres...

Page 147: ...he current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the processor is halted the updated value is used when prefetchin...

Page 148: ...address which the debug module uses to generate a special bus cycle to access the specified control register The 12 bit Rc field is the same as that used by the MOVEC instruction Command Result Forma...

Page 149: ...ongword data is written to the specified control register The write alters all 32 register bits Command Result Formats Command Sequence Figure 5 36 WCREG Command Sequence 15 12 11 8 7 4 3 0 Command 0x...

Page 150: ...ad of the CSR clears CSR FOF TRG HALT BKPT as well as the trigger status bits CSR BSTAT if either a level 2 breakpoint has been triggered or a level 1 breakpoint has been triggered and no level 2 brea...

Page 151: ...s support debugging real time applications For these types of embedded systems the processor must continue to operate during debug The foundation of this area of debug support is that while the proces...

Page 152: ...RC 01 a breakpoint trigger causes the core to halt PST 0xF If the processor core cannot be halted the debug interrupt can be used With this configuration TDR TRC 10 the breakpoint trigger becomes a de...

Page 153: ...e Section 5 5 1 CPU Halt A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when tr...

Page 154: ...ds 5 7 Processor Status DDATA Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction basis In...

Page 155: ...D source PST 0x8 DD destination bra b w PST 0x5 bset imm ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bset Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bsr b w PST 0x5 PST 0xB DD...

Page 156: ...CCR Dx PST 0x1 move w Dy imm CCR PST 0x1 movem l list ea x PST 0x1 PST 0xB DD destination 2 movem l ea y list PST 0x1 PST 0xB DD source 2 moveq imm Dx PST 0x1 msac l Ry Rx PST 0x1 msac l Ry Rx ea Rw...

Page 157: ...T 0x13 trapf PST 0x1 tst b ea x PST 0x1 PST 0x8 DD source operand tst l ea x PST 0x1 PST 0xB DD source operand tst w ea x PST 0x1 PST 0x9 DD source operand unlk Ax PST 0x1 PST 0xB DD destination opera...

Page 158: ...n returns the processor to emulator mode a multiple cycle status of 0xD is signaled Similar to the exception processing mode the stopped state PST 0xE and the halted state PST 0xF display this status...

Page 159: ...connector arranged 2 x 13 Figure 5 41 Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved 1 GND GND RESET Pad Voltage2 GND PST2 PST0 DDATA...

Page 160: ...Debug Support MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 5 42 Freescale Semiconductor...

Page 161: ...the interface between the ColdFire core processor complex and the internal peripheral devices Figure 6 1 SIM Block Diagram SDRAM Controller External Bus Interface SYSTEM INTEGRATION MODULE SIM 32 Bit...

Page 162: ...dware watchdog timer See Section 6 2 3 System Configuration Register SCR Software watchdog timer See Section 6 2 8 Software Watchdog Timer Pin assignment register PAR configures the parallel port See...

Page 163: ...te boundaries If MBAR V is set MBAR BA is compared to the upper 16 bits of the full 32 bit internal address to Table 6 1 SIM Registers MBAR Offset 31 24 23 16 15 8 7 0 0x000 Module base address regist...

Page 164: ...1000_0000 using the D0 register Setting MBAR V validates the MBAR location This example assumes all accesses are valid move 1 0x10000001 DO movec DO MBAR 31 16 15 5 4 3 2 1 0 Field BA SC SD UC UD V Re...

Page 165: ...Priority Selects the bus arbiter priority scheme 0 Ethernet has highest priority DMA has next highest priority CPU has lowest priority 1 CPU has highest priority DMA has next highest priority Ethernet...

Page 166: ...9 8 Field ADC WPV SMV PE HWT RPV EXT SUV Reset 0000_0000 R W R W 7 6 5 4 3 2 1 0 Field ADCEN WPVEN SMVEN PEEN HWTEN RPVEN EXTEN SUVEN Reset 0000_1011 R W R W Address MBAR 0x006 Table 6 4 SPR Field Des...

Page 167: ...access error exception 9 1 EXT EXTEN External transfer error This bit is set when an external transfer error is reported to the SIM on TEA If EXTEN is also set the bus cycle is terminated with an acc...

Page 168: ...IPDN QSPI power down enable Controls the clocking to the QSPI module 0 Clock enabled 1 Clock disabled 20 TIMERPDN Timer power down enable Controls the clocking to the timer module 0 Clock enabled 1 Cl...

Page 169: ...and then execute a STOP instruction See Section 6 2 6 Activate Low Power Register ALPR It is not necessary to put any on chip modules in power down mode After setting this bit a write access must be m...

Page 170: ...on executed after the write to the ALPR Sleep mode is exited by an interrupt request from by either an external device or an on chip peripheral as detailed in Table 6 7 The sequence to enter stop mode...

Page 171: ...ounts until it reaches the reset timeout value resulting in a hardware reset with RSTO driven low for 16 clocks SCR RSTSRC is updated to indicate that the software watchdog caused the reset General pu...

Page 172: ...he software watchdog timeout causing a reset Table 6 9 describes WRRR fields 6 2 8 2 Watchdog Interrupt Reference Register WIRR The watchdog interrupt reference register WIRR Figure 6 9 contains the r...

Page 173: ...When enabled software should periodically write to WCR to avoid reaching the interrupt reference value 0 Disable interrupt 1 Enable interrupt upon reaching interrupt reference value If IEN is set whe...

Page 174: ...System Integration Module SIM MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 6 14 Freescale Semiconductor...

Page 175: ...module QSPI module Software watchdog timer SWT Figure 7 1 is a block diagram of the interrupt controller The SIM provides the following registers for managing interrupts Four interrupt control regist...

Page 176: ...upts should have vectors in the user defined interrupt region of the vector table vectors 64 255 The location of these vectors is programmable through the PIVR For more information on the servicing of...

Page 177: ...lowest priority as shown in Figure 7 8 7 2 1 Interrupt Controller Registers This section describes the registers associated with the interrupt controller Table 7 2 gives the nomenclature used for the...

Page 178: ...INT2PI INT2IPL INT3PI INT3IPL INT4PI INT4IPL Reset 0000_0000_0000_0000 15 14 12 11 10 8 7 6 4 3 2 0 Field TMR0PI TMR0IPL TMR1PI TMR1IPL TMR2PI TMR2IPL TMR3PI TMR3IPL Reset 0000_0000_0000_0000 R W R W...

Page 179: ...RT11IPL UART2PI UART2IPL PLIPPI PLIPIPL PLIAPI PLIAIPL Reset 0000_0000_0000_0000 15 14 12 11 10 8 7 6 4 3 2 0 Field USB0PI USB0IPL USB1PI USB1IPL USB2PI USB2IPL USB3PI USB3IPL Reset 0000_0000_0000_000...

Page 180: ...n Table 7 4 describes ISR fields 31 30 29 28 27 26 25 24 Field INT1 INT2 INT3 INT4 TMR0 TMR1 TMR2 TMR3 Reset XXXX_1111 R W Read only 23 22 21 20 19 18 17 16 Field UART1 UART2 PLI_P PLI_A USB0 USB1 USB...

Page 181: ...t inputs Table 7 5 describes PITR fields 31 30 29 28 27 16 Field INT1 INT2 INT3 INT4 Reset 0000_0000_0000_0000 15 7 6 5 4 0 Field INT5 INT6 Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x034 Figure 7 7...

Page 182: ...interrupts with the priority order following the bit placement in the PIWR with INT1 having the highest priority and SWTO having the lowest priority as shown in Figure 7 8 Table 7 6 describes PIWR fie...

Page 183: ...r in the PIVR The lower five bits are provided by the interrupt controller depending on the source as shown in Table 7 7 If the core initiates an interrupt acknowledge cycle prior to the PIVR being pr...

Page 184: ...TMR0 Timer 0 70 00110 TMR1 Timer 1 71 00111 TMR2 Timer 2 72 01000 TMR3 Timer 3 73 01001 UART1 UART 1 74 01010 UART2 UART 2 75 01011 PLIP PLIC 2KHz Periodic 76 01100 PLIA PLIC Asynchronous 77 01101 US...

Page 185: ...ing for memory block sizes from 4 Kbytes to 2 Gbytes Programmable wait states and port sizes Programmable address setup Programmable address hold for read and write SDRAM controller interface supporte...

Page 186: ...urst capability wait states and read write access Table 8 1 CSCR and CSOR Values after Reset Offset Name Chip Select Register Reset 0x040 CSBR0 CS base register 0 0x0000_0x011 1 The nibble shown as x...

Page 187: ...etermine timing of the appropriate bus interface module onto the device pins 00 16 32 bit SRAM ROM For 16 32 bit wide memory devices with byte strobe inputs CSBR0 EBI 00 at reset Affects all chip sele...

Page 188: ...Interrupt acknowledge level 3 11 100 Interrupt acknowledge level 4 11 101 Interrupt acknowledge level 5 11 110 Interrupt acknowledge level 6 11 111 Interrupt acknowledge level 7 1 CTM Compare TM Enabl...

Page 189: ...ame Description 31 12 BAM Address mask Masks equivalent CSOR BA bits The BAM setting chooses which BA bits to compare with the corresponding address bit to determine a match 0 Mask address bit 1 Compa...

Page 190: ...e the access 0x00 No wait states 0x01 1 wait state 0x1E 30 wait states 0x1F External access For example WS 0x0A introduces a 10 clock wait before the bus cycle terminates 0x1F indicates a source exter...

Page 191: ...lity for different SDRAM sizes with a single printed circuit board layout Page size from 256 1024 column address locations 6 1 1 1 timing for burst read 3 1 1 1 timing for burst write accesses assumin...

Page 192: ...I does not affect the SDRAM controller which continues to refresh external memory This is useful for debug situations where a reset of the device is required without losing data located in SDRAM DRESE...

Page 193: ...nal Descriptions continued Signal Description VDD DQ0 VDD DQ1 DQ2 GND DQ3 DQ4 VDD DQ5 DQ6 GND DQ7 VDD DQML R W CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD GND DQ15 GND DQ14 DQ13 VDD DQ12 DQ11 GND DQ10 DQ9...

Page 194: ...ata Signals 16 Bit 32 Bit 16 Bit 32 Bit 2 x 16 32 Bit 1 x 32 BS3 BS3 DQMH DQMH DQM3 D 31 24 BS2 BS2 DQML DQML DQM2 D 23 16 NC BS1 NC DQMH DQM1 D 15 8 NC BS0 NC DQML DQM0 D 7 0 Table 9 3 Configurations...

Page 195: ...SDBA0 BA0 A21 A22 A20 A21 A22 A23 SDBA1 BA1 A23 A22 A23 A24 Table 9 6 Internal Address Multiplexing 32 Bit Data Bus Device Pin SDRAM Pin 8 Bit 16 Bit 32 Bit 16 Mbits 64 Mbits 16 Mbits 64 Mbits 128 Mbi...

Page 196: ...a page miss After a bank is activated it remains activated until the next page access causing a page miss A precharge of a deactivated bank is allowed and simply ignored by the SDRAM If a memory acce...

Page 197: ...to REG enables pipeline mode for read data access It forces the SDRAM controller to register the read data adding one wait state to single read accesses and to the first word read during a burst REG...

Page 198: ...Table 9 8 SDTR Field Descriptions Bits Name Description 15 10 RTP Refresh timer prescaler Determines the number of clock cycles x 16 between refreshes The following table describes different recommend...

Page 199: ...set after initialization 9 7 Power Down and Self Refresh The SDRAM can be powered down by setting SDCR GSL The SDRAM controller executes the required power down command sequence to ensure self refres...

Page 200: ...vate the new page before the read write access There are no precharge cycles when an address hits an open page In Table 9 9 the timing configuration is RTP 61 RC negligible RCD 0 or 1 RP 1 or 0 and CL...

Page 201: ...1 7 1 Page hit 3 1 3 1 Burst read Page miss 9 1 1 1 1 1 1 1 16 10 1 1 1 1 1 1 1 17 Page hit 5 1 1 1 1 1 1 1 12 6 1 1 1 1 1 1 1 13 Burst write Page miss 7 1 1 1 1 1 1 1 14 7 1 1 1 1 1 1 1 14 Page hit...

Page 202: ...This timing issue cannot be solved by reducing the SDCLK frequency SDCLK must be delayed further to meet setup hold margin on the SDRAM data input Setting INV provides a 180 phase shift and moves the...

Page 203: ...time should be inspected during reads The active clock edge event of SDCLK now precedes the MCF5272 internal active clock edge event when REG 0 This behavior is frequency dependent The two following...

Page 204: ...ne now runs with CAS latency 1 and SDRAMs run with CAS latency 2 which increases bandwidth on the SDRAM bank and improves performance 9 10 SDRAM Interface Setting CSBRn EBI to 0b01 enables chip select...

Page 205: ...r self refreshing sleep mode as shown in Figure 9 14 and Figure 9 15 It is also possible to turn off the SDRAM controller completely using the power management control register in the SIM Figures show...

Page 206: ...2 Bit Port Page Miss Access 9 1 1 1 Col T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Data Data Data Data Row Col Col Col Row Bank x Bank y Bank y SDCLK SDCLKE SDADR 13 0 A10_PRECHG SDBA 1 0 SDCS RAS0...

Page 207: ...takes a clock cycle T2 to determine whether the access is a hit or a miss Because it is a hit the burst operation follows immediately Figure 9 10 SDRAM Burst Read 32 Bit Port Page Hit Access 5 1 1 1 T...

Page 208: ...Figure 9 11 after the SDRAM determines that this is a page miss T2 the precharge old page T3 and activate new page cycles T5 are required Cycle T6 is a wait state for SDRAM activation command as it i...

Page 209: ...RAM controller determines that the access is a page hit in T2 the burst transfer begins in T3 Figure 9 12 SDRAM Burst Write 32 Bit Port Page Hit Access 3 1 1 1 T0 T1 T2 T3 T4 T5 T6 T7 T8 Data Data Dat...

Page 210: ...and T1 the SDRAM writes all of its on chip RAM page buffers into the SDRAM array SDTR RP determines the number of dead cycles after a precharge Note that self refresh occurs during T3 In refresh state...

Page 211: ...the SDRAM array The SDTR RP value determines the number of dead cycles after a precharge Note that auto refresh occurs in T3 SDTR RC determines the number of clock cycles the SDRAM remains in refresh...

Page 212: ...ode Note that SDCR GSL is sampled on the rising edge of the internal clock If it is 0 as it is here SDRAM controller signals become active on the following negative clock edge Figure 9 15 Exit SDRAM S...

Page 213: ...estinations can be SDRAM external SRAM or on chip peripheral in any combination NOTE Memory to memory DMA transfers run to completion if the assume request bit in the system configuration register SCR...

Page 214: ...s various operation modes principally the request and addressing modes Fields include the transfer size and modifier transfer direction channel enable and reset Table 10 2 describes DMR fields 31 30 2...

Page 215: ...ffers data from the source address data fetches until there are enough bytes to perform a destination data write of the size programmed in these bits Thus it is possible to configure source accesses t...

Page 216: ...thod is to use longword or line burst transfer types SRCS Data Transfer Type Address Incremented by 00 Longword 4 01 Byte 1 10 Word 2 11 16 byte line burst 16 Valid only for SDRAM 15 13 12 11 10 9 8 7...

Page 217: ...iting a 0 has no effect No further transfers can take place when ASC is set It is important to ensure that the combination of source address destination address and transfer sizes ensures that the byt...

Page 218: ...h the number of bytes to be transferred during the DMA After each transfer the DBCR decrements by the number of bytes transferred DIR ASC is set when the byte counter reaches zero The user must ensure...

Page 219: ...features Full compliance with the IEEE 802 3 standard Support for three different physical interfaces 100 Mbps 802 3 media independent interface MII 10 Mbps 802 3 MII 10 Mbps seven wire interface Half...

Page 220: ...FO Shifter Tx Transmitter Control Unit FIFO Slot Time Clock Generator Internal Clocks Control Registers TXD RXD Peripheral Bus Data Data RCLK TCLK and Defer Counter RTS TENA CD RENA CTS CLSN CTS CLSN...

Page 221: ...sical layer device to pass control and status information The descriptor controller manages data flow in both transmit and receive directions It is programmed with microcode to open and close buffer d...

Page 222: ...asserts E_TxEN and starts transmitting the preamble sequence the start of frame delimiter and then the frame data However if the line is busy the controller defers the transmission carrier sense is a...

Page 223: ...s not truncated See Section 11 5 14 Maximum Frame Length Register MFLR Both buffer and frame interrupts may be generated as determined by the EIMR register settings Setting the graceful transmit stop...

Page 224: ...reception the FEC checks for a frame that is either too short or too long When the frame ends carrier sense is negated the receive CRC field is checked and written to the data buffer The data length w...

Page 225: ...ognition Flowchart Table 11 3 Ethernet Address Recognition Destination Address Type FEC Address Processing individual The FEC compares the destination address field of the received frame with the 48 b...

Page 226: ...back transmission is 96 bit times After completing a transmission or after the backoff algorithm completes the transmitter waits for carrier sense to negate before starting its interpacket gap time co...

Page 227: ...frame are then flushed and closed with the LC bit set in the last TxBD for that frame The FEC then continues to the next TxBD and begins sending the next frame Heartbeat Some transceivers have a self...

Page 228: ...nterrupt mask register p 11 13 0x84C IVSR 32 Interrupt vector status register p 11 14 0x850 RDAR 32 Receive descriptor active register p 11 15 0x854 TDAR 32 Transmit descriptor active register p 11 16...

Page 229: ...that have hold time requirements that exceed the MII specification 24 2 Reserved should be cleared 1 ETHER_EN Ethernet enable When this bit is set the FEC is enabled and reception and transmission is...

Page 230: ...tted frame length has exceeded MAX_FL bytes This condition is usually caused by a frame that is too long being placed into the transmit data buffer s Truncation does not occur 28 GRA Graceful stop com...

Page 231: ..._0000 R W Read write Addr MBAR 0x848 Figure 11 7 Interrupt Mask Register EIMR Table 11 9 EIMR Register Field Descriptions Bits Name Description 31 22 See Figure 11 7 Interrupt mask Each bit correspond...

Page 232: ...0 R W Read Only 15 4 3 2 1 0 Field IVEC Reset 0000_0000_0000_0000 R W Read Only Addr MBAR 0x84C Figure 11 8 Interrupt Vector Status Register IVSR Table 11 10 IVSR Field Descriptions Bit Name Descripti...

Page 233: ...es provided ETHER_EN is also set As soon as the FEC polls a receive descriptor whose E bit is not set it clears the R_DES_ACTIVE bit and stops polling the receive descriptor ring The RDAR register is...

Page 234: ...provided ETHER_EN is also set As soon as the FEC polls a transmit descriptor whose ready bit is not set it clears the X_DES_ACTIVE bit and stops polling the transmit descriptor ring The TDAR register...

Page 235: ...802 3 compliant MII management interface write frame write to a PHY register the user must write 01 01 PHYAD REGAD 10 DATA to the MMFR register Writing this pattern causes the control logic to shift...

Page 236: ...MII Speed Control Register MSCR The MSCR register Figure 11 12 provides control of the MII clock E_MDC pin frequency allows dropping the preamble on the MII management frame and provides observability...

Page 237: ...unction of system clock frequency 11 5 9 FIFO Receive Bound Register FRBR FRBR is a read only register used to determine the upper address boundary of the FIFO RAM Drivers can use this value along wit...

Page 238: ...register must be added to MBAR 0x800 to determine the absolute address FRSR needs to be written only to change the default value Table 11 17 describes the FRSR fields 31 16 Field Reset 0000_0000_0000...

Page 239: ...0000_0000_0000_0000 R W Read Write 15 2 1 0 Field X_WMRK Reset 0000_0000_0000_00 00 R W Read Write Addr MBAR 0x8E4 Figure 11 15 Transmit FIFO Watermark TFWR Table 11 18 TFWR Field Descriptions Bits N...

Page 240: ...n this register must be added to MBAR 0x800 to determine the absolute address The TFSR register is reset to the first available RAM address Table 11 19 describes the TFSR fields 31 16 Field Reset 0000...

Page 241: ...epted regardless of address matching 2 MII_MODE MII mode enable Selects the external interface mode Setting this bit to one selects MII mode setting this bit equal to zero selects seven wire mode used...

Page 242: ...ceive frame contained a destination address of all ones the broadcast address Cleared if the current receive frame does not correspond to a broadcast address 30 MULTCAST Multicast address received Set...

Page 243: ...heartbeat check is performed following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window This bit should be modified o...

Page 244: ...h the Destination Address field of the receive frames This register shown in Figure 11 20 is not reset and must be initialized by the user prior to operation 31 16 Field ADDR_LOW Reset Undefined R W R...

Page 245: ...f the receive frames Byte 0 is the first byte transmitted on the network at the start of the frame This register is not reset and must be initialized by the user prior to operation See Figure 11 21 31...

Page 246: ...reset and must be initialized by the user prior to operation 31 16 Field HASH_HIGH Reset Undefined R W Read Write 15 0 Field HASH_HIGH Reset Undefined R W Read Write Addr MBAR 0xC08 Figure 11 22 Hash...

Page 247: ...t reset and must be initialized by the user prior to operation 31 16 Field HASH_LOW Reset Undefined R W Read Write 15 0 Field HASH_LOW Reset Undefined R W Read Write Addr MBAR 0xC0C Figure 11 23 Hash...

Page 248: ...divisible by 16 in order to improve bus utilization Bits 1 and 0 should be written to 0 by the user Non zero values in these two bit positions are ignored by the hardware This register is not reset a...

Page 249: ...sible by 16 in order to improve bus utilization Bits 1 and 0 should be set to 0 by the user Non zero values in these two bit positions are ignored by the hardware This register is not reset and must b...

Page 250: ...BUFF_SIZE must be set to MAX_FL or larger The R_BUFF_SIZE must be evenly divisible by 16 To insure this bits 3 0 are forced low To minimize bus utilization descriptor fetches it is recommended that R_...

Page 251: ...ever the ETHER_EN bit is cleared Clearing ETHER_EN immediately stops all DMA and transmit activity after a bad CRC is sent as shown in Table 11 31 11 5 23 User Initialization Prior to Asserting ETHER_...

Page 252: ...though these could also be done before asserting ETHER_EN 11 6 Buffer Descriptors Data associated with the FEC controller is stored in buffers which are referenced by buffer descriptors BDs organized...

Page 253: ...buffer descriptors are not initialized by hardware during reset At least one transmit and receive BD must be initialized by software write 0x0000_0000 to the most significant word of buffer descriptor...

Page 254: ...ceived because of promiscuous mode 7 BC Broadcast Written by the FEC Will be set if DA is broadcast FF FF FF FF FF FF 6 MC Mulitcast Written by the FEC Is set if DA is multicast and not BC 5 LG Rx fra...

Page 255: ...0 The data buffer associated with this BD is not ready for transmission The user is free to manipulate this BD or its associated data buffer The FEC clears this bit after the buffer has been transmitt...

Page 256: ...and is valid only if L 1 These four bits indicate the number of retries required before this frame is successfully transmitted If RC 0 then the frame was transmitted correctly the first time If RC 15...

Page 257: ...big endian mode is supported for buffer descriptors and buffers Separate interrupt vectors for Rx Tx and non time critical interrupts Interrupt priority is set in the interrupt controller The formula...

Page 258: ...Ethernet Module MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 11 40 Freescale Semiconductor...

Page 259: ...ost scheduled token based protocol The USB uses a tiered star topology with a hub at the center of each star as shown in Figure 12 1 Each wire segment is a point to point connection between the host A...

Page 260: ...nsists of a protocol state machine which controls the transmitter and receiver modules The state machine implements only the USB function state diagram The MCF5272 USB controller can serve as a USB fu...

Page 261: ...d in the Chapter 7 of the Universal Serial Bus Specification See note on page p 12 1 When the internal transceiver is selected USBEPCTL0 AFEEN is cleared the driven outputs can be observed by using th...

Page 262: ...pin during system reset This automatic selection can be overridden by setting bit USBEPCTL0 CLK_SEL If a clock signal is not present on USB_CLK the clock generator uses the system clock NOTE In all c...

Page 263: ...request is passed to the user as a vendor specific request The USB module responds with a request error when the SET_DESCRIPTOR request is issued These standard requests are defined in Chapter 9 of t...

Page 264: ...equest completes successfully and must initialize the active endpoint controllers set_descriptor Not supported Returns request error set_feature Sets the specified feature Remote wakeup and endpoint h...

Page 265: ...ice Request Data1 Register DRR1 0x101C USB Device Request Data2 Register DRR2 0x1020 Reserved USB Specification Number Register SPECR 0x1024 Reserved USB Endpoint 0 Status Register EP0SR 0x1028 USB En...

Page 266: ...r EP4IMR 0x10A0 Reserved USB Endpoint 5 Interrupt Mask Register EP5IMR 0x10A4 Reserved USB Endpoint 6 Interrupt Mask Register EP6IMR 0x10A8 Reserved USB Endpoint 7 Interrupt Mask Register EP7IMR 0x10A...

Page 267: ...he FNMR Figure 12 4 byte accesses to this register are not supported and cause an access error Figure 12 4 USB Frame Number Match Register FNMR Table 12 4 describes FNMR fields 15 11 10 0 Field FRM Re...

Page 268: ...erifying that the same value is seen on the higher order bits for two consecutive read cycles Figure 12 5 shows the USB real time frame monitor register Figure 12 5 USB Real Time Frame Monitor Registe...

Page 269: ...This value is for information only Figure 12 7 USB Function Address Register FAR Table 12 7 gives the USB function address register field descriptions 15 14 13 0 Field RTFM_MAT Reset 0011_1111_1111_1...

Page 270: ...e 12 8 lists field descriptions for the USB alternate settings register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field IF15_AS IF14_AS IF13_AS IF12_AS IF11_AS IF10_AS IF9_AS IF8_AS Reset 0000_0...

Page 271: ...eceived and to pass the request type and parameters to the application The fields in DRR1 and DRR2 are defined in Chapter 9 of the USB Specification See top of page p 12 1 Figure 12 9 USB Device Reque...

Page 272: ...ce complies with The USB Specification Release Number is in binary coded decimal BCD format 3 0 MRN Module revision number 15 12 11 10 3 2 1 0 Field CONFIG WAKE_ST HALT_ST DIR Reset 0000_0000_0000_000...

Page 273: ...figured as an IN endpoint 0 The endpoint is configured as an OUT endpoint 0 Reserved should be cleared 31 22 21 20 16 Field MAX_PACKET FIFO_SIZE Reset 0000_0000_0000_0000 R W R W 15 11 10 9 0 Field FI...

Page 274: ...e USB endpoint 1 7 configuration register See Table 12 11 for a description of the fields 31 22 21 20 16 Field MAX_PACKET FIFO_SIZE Reset 0000_0000_0000_0000 R W R W 15 11 10 9 0 Field FIFO_SIZE FIFO_...

Page 275: ...UG Debug mode Enters debug mode Debug mode enables CRC error generation and notification of a change of address 0 Normal operation 1 Enable debug mode functions 17 WOR_LVL Wake on ring level select Se...

Page 276: ...uld be set after USB module registers are initialized and the descriptors are copied into the configuration RAM 0 Disable USB module 1 Enable USB module 10 CFG_RAM_VAL Enable USB configuration RAM Not...

Page 277: ...FIFO 50 Empty 10 FIFO 75 Empty 11 FIFO 100 Empty 1 IN_DONE This bit controls the USB s response to IN tokens from the host This bit is set at Reset and must be cleared by software when the last byte...

Page 278: ...st purposes To use this feature the DEBUG bit must be set Enabling this bit causes a CRC error on the next non zero length data packet transmitted The CRC_ERR bit must be set again in order to generat...

Page 279: ...the previously transmitted IN packet was full and no more data remains in the IN FIFO Hence a single zero length packet must be sent to indicate EOT 0 CPU has completed writing to the IN FIFO and tra...

Page 280: ...OP OUT_LVL IN_EOT IN_EOP UNHALT HALT IN_LVL Reset 0000_0000 R W R W Addr MBAR 0x108C EP0IMR MBAR 0x106C EP0ISR Figure 12 18 USB Endpoint 0 Interrupt Mask EP0IMR and General Endpoint 0 Interrupt Regist...

Page 281: ...ted 0 No interrupt pending 1 USB resume signal detected 9 SUSPEND Suspend Set when the USB module detects a suspend state on the USB data lines The USB suspends when the bus is idle for at least 3 ms...

Page 282: ...n a packet has been sent successfully for endpoint 0 IN 0 No interrupt pending 1 IN packet sent successfully 2 UNHALT Unhalt This bit is set when the endpoint 0 HALT_ST bit is cleared by a SETUP packe...

Page 283: ...int n This bit indicates whether endpoint n is currently configured as an IN or OUT endpoint 0 Endpoint n configured as an OUT endpoint 1 Endpoint n configured as an IN endpoint 13 PRES Endpoint n pre...

Page 284: ...ched interrupt Indicates that the FIFO level has risen above or fallen below the level set in the EPCTLn register for OUT or IN endpoints respectively 0 No interrupt pending 1 FIFO threshold level rea...

Page 285: ...15 0 Field DATA Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x10AC 0x10B0 0x10B4 0x10B8 0x10BC 0x10C0 0x10C4 0x10C8 Figure 12 21 USB Endpoint 0 7 Data Registers EPnDR Bits Name Description 31 0 DATA T...

Page 286: ...d any relevant class specification NOTE The USB descriptors use little endian format for word and longword fields The MCF5272 uses big endian format for words and longwords The user must make sure tha...

Page 287: ...any time 12 3 3 2 USB Device Configuration Example The example descriptor structure in Figure 12 23 shows a device with three different configurations Refer to Chapter 9 of the USB Specification for...

Page 288: ...es and whether the previous FIFO access was for the same endpoint After a longword access to an endpoint s FIFO the next longword in the FIFO is cached for a quicker access time on the next longword r...

Page 289: ...in EP0ISR 7 Enable the desired EP0 interrupt sources in EP0IMR 8 Set EP0CTL USB_EN CFG_RAM_VALID 12 4 2 USB Configuration and Interface Changes Although the USB module handles the SET_CONFIGURATION an...

Page 290: ...O_ADDR must not overlap with the FIFO space for any other endpoint with the same direction An example FIFO configuration with a variety of endpoint types and packet sizes is shown in Table 12 20 12 4...

Page 291: ...until all of the data for the transfer has been written to the FIFO 7 Clear EPnCTL IN_DONE 8 Wait for the EOT interrupt or poll the EOT bit The user can now begin processing the next transfer 12 4 4 1...

Page 292: ...size 1 Wait for the SOF interrupt for synchronization 2 Write data to the FIFO until filled 3 Wait for FIFO_LVL interrupt 4 Read EPnDP to determine the number of bytes that can be written to the FIFO...

Page 293: ...at the active level defined in EP0CTL The USB module responds to the INT1 pin only if the wake on ring function is enabled the USB is in the suspended state and EP0SR WAKE_ST is set The ColdFire core...

Page 294: ...discrete components The recommended circuit for implementing software control of the pull up resistor is shown in Figure 12 24 12 5 2 PCB Layout Recommendations The device has input protection on all...

Page 295: ...e GND leads A PCB with a ground plane connecting all of the digital and analog GND pins together is the optimal ground configuration producing the lowest resistance and inductance in the ground circui...

Page 296: ...Universal Serial Bus USB MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 12 38 Freescale Semiconductor...

Page 297: ...rvices digital network interfaces The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN transceivers codecs and other peripherals There are three sets of pins f...

Page 298: ...rates as a slave only port Port 2 shares a data clock with port 1 DCL1 when port 1 is in slave mode or GDCL when port 1 is in master mode A delayed frame sync DFSC2 derived from FSC1 is connected to t...

Page 299: ...13 2 1 GCI IDL B and D Channel Receive Data Registers Figure 13 2 GCI IDL Receive Data Flow The maximum data rate received for each GCI IDL port is 144 Kbps the sum of two 64 Kbps B channels and one...

Page 300: ...64 Kbps B channels and one 16 Kbps D channel Frames of B1 B2 and D channels are packed together in a similar way to the receive side Because the reception and transmission of information on the GCI I...

Page 301: ...data appears on the physical interface most significant bit msb first the msb is left aligned in the transmit and receive shift register that is the first bit of B channel received data is aligned in...

Page 302: ...received bit of a byte that is aligned in the msb position The ordering of the bytes over four frames within the longword register is as for unencoded data that is the first frame is aligned in the MS...

Page 303: ...oded PCM encoded B channel data it is assumed unencoded D channel information is presented on the physical line msb first The msb is left aligned in the transmit and receive shift register that is the...

Page 304: ...ntention such as the indirect mode found on the Freescale MC145574 In GCI mode the DGRANT pin function found in IDL mode is disabled and the pin can be defined for other functions Please note that the...

Page 305: ...y the transmitter clock 13 2 4 3 Remote Loopback Mode The channel automatically transmits received data on the transmit Dout pin on a bit by bit basis in this mode The local CPU to transmitter link is...

Page 306: ...port and individual interrupts within each port is maskable The following conditions for each of the ports can trigger this interrupt Monitor channel receive ASR defines which port or ports have gene...

Page 307: ...is always an integral power of two between 2 and 256 inclusive The amount of phase jitter exhibited by the synthesized clock increases as the synthesized clock frequency approaches CLKIN s frequency...

Page 308: ...3 12 show the connectivity and relationship of the timing signals within the PLIC block Figure 13 11 PLIC Internal Timing Signal Routing Figure 13 12 PLIC Clock Generator Port 0 Port 1 Port 2 Port 3 P...

Page 309: ...ed to DFSC0 DFSC2 and DFSC3 are generated through programmable delays 2 and 3 referenced to DFSC1 Note well the following P0SDR settings affect DFSC 0 3 P1SDR settings affect DFSC 1 3 P2SDR settings a...

Page 310: ...P2GMR Port3 GCI monitor Rx P3GMR 0x0368 Port0 GCI monitor Tx P0GMT Port1 GCI monitor Tx P1GMT 0x036C Port2 GCI monitor Tx P2GMT Port3 GCI monitor Tx P3GMT 0x0370 Reserved GCI monitor Tx status PGMTS G...

Page 311: ...and are set on hardware or software reset The PnB1RRs contain the last four frames of data received on channel B1 P0B1RR is the B1 channel data for port 0 P1B1RR is B1 for port 1 and so on The data a...

Page 312: ...re or software reset The PnDRR registers contain the last four frames of D channel receive data packed from the least significant bit lsb to the most significant bit msb for each of the four physical...

Page 313: ...hardware or software reset The PnB2TR registers contain four frames of transmit data for port n of channel B2 P0B2TR is the B2 channel transmit data for port 0 P1B2TR is B2 transmit for port 1 and so...

Page 314: ...the MSB of the PLTD register P3DTR is located in the LSB of the PLTD register 13 5 7 Port Configuration Registers P0CR P3CR PnCR are registers containing configuration information for each of the four...

Page 315: ...is generated from port 0 1 Port 1 FSC FSR is used to generate the 2 KHz interrupt 8 ACT GCI Activation 0 Default reset value 1 Causes Dout to transition to a logic low for the respective port This bi...

Page 316: ...elay Registers P0SDR P3SDR 13 5 9 Interrupt Configuration Registers P0ICR P3ICR All bits in these registers are read write and are cleared on hardware or software reset The PnICR registers contain int...

Page 317: ...for the monitor channel transmit 0 Interrupt masked 1 Interrupt enabled 7 6 Reserved should be cleared 5 DTIE D transmit interrupt enable 0 Interrupt masked 1 Interrupt enabled Interrupt occurs when t...

Page 318: ...when the PnPSR register has been read by the CPU 8 DROE D Channel data receive overrun error This bit is set when the data in the D receive shadow register for the respective port has been transferre...

Page 319: ...PASR Field Descriptions Bits Name Description 15 11 7 3 GCRn GCI C I received When set this bit indicates that valid new data has been written to a GCI C I receive register An interrupt is queued when...

Page 320: ...P3GMR Figure 13 24 GCI Monitor Channel Receive Registers P0GMR P3GMR Table 13 7 P0GMR P3GMR Field Descriptions Bits Name Description 15 11 Reserved should be cleared 10 EOM End of message 0 Default a...

Page 321: ...ters P0GMT P3GMT Table 13 8 P0GMT P3GMT Field Descriptions Bits Name Description 15 10 Reserved should be cleared 9 L Last 0 Default reset value 1 Set by the CPU Indicates to the monitor channel contr...

Page 322: ...6 5 4 3 0 Field AR3 AR2 AR1 AR0 Reset 0000_0000 R W Read Write Addr MBAR 0x372 Figure 13 26 GCI Monitor Channel Transmit Abort Register PGMTA Table 13 9 PGMTA Field Descriptions Bits Name Description...

Page 323: ...Acknowledge port 3 0 Default reset value 1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel information Automatically cleared by the CPU reading the register...

Page 324: ...GCIR 0x375 P1GCIR 0x376 P2GCIR 0x377 P3GCIR Figure 13 28 GCI C I Channel Receive Registers P0GCIR P3GCIR Table 13 11 P0GCIR P3GCIR Field Descriptions Bits Name Description 31 29 23 21 15 13 7 5 Reserv...

Page 325: ...e 13 12 P0GCIT P3GCIT Field Descriptions Bits Name Description 31 29 23 21 15 13 7 5 Reserved should be cleared 28 20 12 4 R Ready This bit is set by the CPU to indicate to the C I channel controller...

Page 326: ...72 7 4 3 2 1 0 Field ACK3 ACK2 ACK1 ACK0 Reset 0000_0000 R W Read Only Addr MBAR 0x37F Figure 13 30 GCI C I Channel Transmit Status Register PGCITSR Table 13 13 PGCITSR Field Descriptions Bits Name De...

Page 327: ...ld be cleared 5 DG1 D channel grant port 1 0 Default reset value 1 In IDL mode indicates the status of DGRANT When the external DGNT has a logic 1 the corresponding DG1 DG0 bit is set In GCI mode DG1...

Page 328: ...received is assumed to be the most significant bit and is loaded into the msb position of the D channel receive register for the respective port SHDD 1 configures the shift direction for ports 1 2 and...

Page 329: ...ot be confused with long frame sync mode The PLIC only supports short frame sync in IDL8 and IDL10 bit modes for interfacing to external transceivers 15 14 13 10 9 0 Field FSW1 FSW0 SD Reset 0000_0000...

Page 330: ...r PCSR Table 13 17 PCSR Field Descriptions Bits Name Description 15 NBP Non bypass mode select for the clock generation module 0 The clock generation module is bypassed Gen_FSC and GDCL are connected...

Page 331: ...ecify which ports are active Specify the operational modes IDL8 IDL10 and so on for the active ports PnCR M If GCI mode is specified in PnCR M select whether GCI SCIT mode is to be used PnCR G S If po...

Page 332: ...Regs_Addr EQU 0x00300000 address of on chip registers P1CR EQU 0x352 offset of P1CR register P1ICR EQU 0x35A move l Module_Regs_Addr A5 reference register from A5 move w 0x9200 d0 port 1 config ON IDL...

Page 333: ...mple then the following configuration would enable periodic interrupts on port 1 with only the D channel active Figure 13 36 Port 1 Interrupt Configuration Register P1ICR The programming of the P1ICR...

Page 334: ...iver are shown The S T transceiver in this example is connected to port 0 and the FSC0 frame sync signal is used exclusively for synchronizing the data on the transceiver s IDL interface CODECs 1 and...

Page 335: ...DCL0 FSC0 and also feed port 1 DCL1 and FSC1 because port 1 is synchronized to these S T generated timing signals The six CODECs are connected to Din1 and Dout1 To provide six discrete 64 Kbps channel...

Page 336: ...face CODECs 1 and 2 are connected to delayed frame sync 2 DFSC2 which is the output of programmable delay 2 Programmable delay 2 generates a delayed frame sync with reference to FSC1 Similarly CODECs...

Page 337: ...r 0x0014 The DFSC3 signal synchronizes CODECs 3 and 4 and the rising edge of this frame sync occurs 20 clocks after DFSC2 therefore 40 DCL clocks after FSC1 This defines the value for programmable del...

Page 338: ...cted to ports 0 and 1 The frame sync control signal FSC0 is connected to S T transceiver one while FSC1 is connected to transceiver two Figure 13 42 shows an example of the IDL bus timing relationship...

Page 339: ...RAMs in the QSPI are indirectly accessible using address and data registers Functionality is very similar but not identical to the QSPI portion of the QSM queued serial module implemented in the MC683...

Page 340: ...agram Queue Control Block Queue Pointer CLKIN 4 Done Comparator End Queue Pointer Status Regs Delay Counter Control Logic Control Regs 80 Byte QSPI RAM Chip Select Command Divide by 2 Baud Rate Genera...

Page 341: ...mode register QMR MSTR must be set for the QSPI to function properly The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI masters 14 4 Operation The QSPI uses...

Page 342: ...led QWR NEWQP and QWR ENDQP can be written at any time When the QWR NEWQP value changes the internal pointer value also changes unless a transfer is in progress in which case the transfer completes no...

Page 343: ...d in the least significant bits of the RAM Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry NOTE Throughout ColdFire documentation word is used consis...

Page 344: ...e Queue execution proceeds from the address in QWR NEWQP through the address in QWR ENDQP The QSPI executes a queue of commands defined by the control bits in each command RAM entry which sequence the...

Page 345: ...al A delay can also be inserted between consecutive transfers to allow serial A D converters to complete conversion There are two transfer delay options the user can choose to delay a standard period...

Page 346: ...bit in the command RAM is set the QSPI_CS signals are asserted between transfers When CONT is cleared QSPI_CS 0 3 are negated between transfers The QSPI_CS signals are not high impedance When the QSP...

Page 347: ...fer size are determined by this register The data output high impedance enable DOHIE controls the operation of QSPI_Dout between data transfers When DOHIE is cleared QSPI_Dout is actively driven betwe...

Page 348: ...is logic level 1 8 CPHA Clock phase Defines the QSPI_CLK clock phase 0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK 1 Data changed on the leading edge of...

Page 349: ...cription 15 SPE QSPI enable When set the QSPI initiates transfers in master mode by executing commands in the command RAM Automatically cleared by the QSPI when a transfer completes The user can also...

Page 350: ...pointed to by QWR NEWQP and continue execution 13 WRTO Wraparound location Determines where the QSPI wraps to in wraparound mode 0 Wrap to RAM entry zero 1 Wrap to RAM entry pointed to by QWR NEWQP 12...

Page 351: ...rved should be cleared 12 ABRTL Abort lock out When set QDLYR SPE cannot be cleared by writing to the QDLYR QDLYR SPE is only cleared by the QSPI when a transfer completes 11 WCEFE Write collision int...

Page 352: ...14 5 5 QSPI Address Register QAR The QAR shown in Figure 14 9 is used to specify the location in the QSPI RAM that read and write operations affect 14 5 6 QSPI Data Register QDR The QDR shown in Figur...

Page 353: ...Chip selects remain asserted between transfers for a transfer of up to 16 words of data 1 1 In order to keep the chip setects asserted for all transfers the QWR CSIV bit must be set to control the le...

Page 354: ...ith the desired delays 4 Write QIR with 0xD00D to enable write collision abort bus errors and clear any interrupts 5 Write QAR with 0x0020 to select the first command RAM entry 6 Write QDR with 0x7E00...

Page 355: ...t of four identical independent 16 bit timers timers 0 3 For timers 0 and 1 the clock input to the prescaler is selected from the main clock divided by 1 or 16 or from the corresponding timer input TI...

Page 356: ...e is selected by the capture edge bits TMR CE A capture or reference event sets the TER bit and generates a maskable interrupt Data 16 Timer Clock Generator Divider Timer Mode Register TMR0 Prescaler...

Page 357: ...vent 11 Capture on any edge and generate interrupt on capture event 5 OM Output mode TMR0 and TMR1 only Reserved in TMR2 and TMR3 0 Active low pulse for one system clock cycle 15 nS at 66 MHz 1 Toggle...

Page 358: ...ting A write cycle to a TCN register causes it to be cleared 0 RST Reset timer 0 A transition from 1 to 0 resets the timer Other register values can be written The counter timer prescaler are not cloc...

Page 359: ...ribes TERn fields 15 2 1 0 Field REF CAP Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x210 TER0 0x230 TER1 0x250 TER2 0x270 TER3 Figure 15 6 Timer Event Registers TER0 TER3 Table 15 2 TERn Fiel...

Page 360: ...Timer Module MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 15 6 Freescale Semiconductor...

Page 361: ...unication channel provides a full duplex asynchronous synchronous receiver and transmitter deriving an operating frequency from CLKIN or an external clock of the correct frequency URT_CLK The transmit...

Page 362: ...overrun error detection False start bit detection Line break detection and generation Detection of breaks originating in the middle of a character Start end break interrupt status Autobaud capability...

Page 363: ...ers URBn p 16 10 UART Write UART transmitter buffers UTBn p 16 11 0x110 0x150 Read UART input port change registers UIPCRn p 16 11 Write UART auxiliary control registers1 UACRn p 16 12 0x114 0x154 Rea...

Page 364: ...Read Do not access 2 Write UART output port bit set command registers UOP1n3 p 16 18 0x13C 0x17C Read Do not access 2 Write UART output port bit reset command registers UOP0n3 p 16 18 1 UMR1n UMR2n a...

Page 365: ...Fn RXS 5 ERR Error mode Configures the FIFO status bits USRn RB FE PE 0 Character mode The USRn values reflect the status of the character at the top of the FIFO ERR must be 0 for correct A D flag inf...

Page 366: ...in the channel transmitter shift and holding registers are completely sent including the programmed number of stop bits 4 TxCTS Transmitter clear to send If both TxCTS and TxRTS are enabled TxCTS con...

Page 367: ...No parity error occurred 1 If UMR1n PM 0x with parity or force parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM 11 multidrop PE stores the received A D bit...

Page 368: ...eived and the receiver FIFO is now full Any characters received when the FIFO is full are lost 0 RxRDY Receiver ready 0 The CPU has read the receiver buffer and no characters remain in the FIFO after...

Page 369: ...command 001 reset mode register pointer Causes the mode register pointer to point to UMR1n 010 reset receiver Immediately disables the receiver clears USRn FFULL RxRDY and reinitializes the receiver...

Page 370: ...itter is disabled transmission completes before the transmitter becomes inactive If the transmitter is already disabled the command has no effect 11 Reserved do not use 1 0 RC This field selects a sin...

Page 371: ...Figure 16 9 hold the current state and the change of state for CTS Table 16 7 describes UIPCRn fields 7 0 Field TB Reset 0000_0000 R W Write only Address MBAR 0x10C 0x14C Figure 16 8 UART Transmitter...

Page 372: ...T module is reset 7 3 2 1 0 Field RTSL IEC Reset 0000_0000 R W Write only Address MBAR 0x110 UACR0 0x150 UACR1 Figure 16 10 UART Auxiliary Control Registers UACRn Table 16 8 UACRn Field Descriptions B...

Page 373: ...d in URFn RXS 4 TxFIFO Transmitter FIFO status After being set this bit is cleared by writing UTBn 0 FIFO status indication is disabled or the transmitter status has not changed 1 The transmitter stat...

Page 374: ...16 3 12 UART Autobaud Registers UABUn UABLn The UABUn registers hold the MSB and the UABLn registers hold the LSB of the calculated baud rate If UCRn ENAB is set the value in these registers is autom...

Page 375: ...ter status When written to these bits control the meaning of UISRn TxFIFO 00 Inhibit transmitter FIFO status indication in UISRn 01 Transmitter FIFO 25 empty 10 Transmitter FIFO 50 empty 11 Transmitte...

Page 376: ...Receiver status When written to these bits control the meaning of UISRn RxFIFO 00 Inhibit receiver FIFO status indication in UISRn 01 Receiver FIFO 25 full 10 Receiver FIFO 50 full 11 Receiver FIFO 75...

Page 377: ...16 12 describes UFPDn fields 16 3 16 UART Input Port Registers UIPn The UIP registers Figure 16 19 show the current state of the CTS input Table 16 13 describes UIPn fields 7 4 3 0 Field FD Reset 0000...

Page 378: ...ld RTS Reset 0000_0000 R W Write only Addr UART0 MBAR 0x138 UOP1 0x13C UOP0 UART1 0x178 UOP1 0x17C UOP0 Figure 16 20 UART Output Port Command Registers UOP1 UOP0 Table 16 14 UOP1 UOP0 Field Descriptio...

Page 379: ...4 bit divider UDU UDL UFPD dedicated to the UART The clock generator cannot produce standard baud rates if CLKIN is used so the 16 bit divider should be used Table 16 15 UART Module Signals Signal De...

Page 380: ...the 4 bit value programmed in UFPDn Note that when autobaud mode is enabled the UFPDn UDUn and UDLn are automatically loaded with the calculated baud rate However the calculated value can be overridd...

Page 381: ...searches for a low level on URT_RxD indicating a start bit Start bit length is measured until URT_RxD returns to a high level then the transmission rate is calculated and loaded into UDUn UDLn and UF...

Page 382: ...o accept a character the UART sets USRn TxRDY The transmitter converts parallel data from the CPU to a serial bit stream on TxD It automatically sends a start bit followed by the programmed number of...

Page 383: ...mpletes RTS must be asserted manually before a message is sent In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed RTS is negated on...

Page 384: ...nd USRn RxRDY is set If the character is less than eight bits the most significant unused bits in the receiver holding register are cleared After the stop bit is detected the receiver immediately look...

Page 385: ...register UMR1n status is provided in character or block modes USRn RxRDY is set when at least one character is available to be read by the CPU A read of the receiver buffer produces an output of data...

Page 386: ...tting device NOTE The receiver can still read characters in the FIFO stack if the receiver is disabled If the receiver is reset the FIFO stack RTS control all receiver status bits and interrupt reques...

Page 387: ...he first character received is correctly echoed back 16 5 3 2 Local Loop Back Mode Figure 16 28 shows how TxD and RxD are internally connected in local loop back mode This mode is for testing the oper...

Page 388: ...repeats the process Functional timing information for multidrop mode is shown in Figure 16 30 A character sent from the master station consists of a start bit a programmed number of data bits an addre...

Page 389: ...te cycles to read only or reserved registers complete normally without exception processing but data is ignored 16 5 5 3 Interrupt Acknowledge Cycles An internal interrupt request signal notifies the...

Page 390: ...dy Receiver never ready Parity error Incorrect character received I O driver routine This routine sheets 4 and 5 consists of INCH the terminal input character routine which gets a character from the r...

Page 391: ...UART Modules MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 Freescale Semiconductor 16 31 Figure 16 31 UART Mode Programming Flowchart Sheet 2 of 5...

Page 392: ...UART Modules MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 16 32 Freescale Semiconductor Figure 16 31 UART Mode Programming Flowchart Sheet 3 of 5...

Page 393: ...UART Modules MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 Freescale Semiconductor 16 33 Figure 16 31 UART Mode Programming Flowchart Sheet 4 of 5...

Page 394: ...UART Modules MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 16 34 Freescale Semiconductor Figure 16 31 UART Mode Programming Flowchart Sheet 5 of 5...

Page 395: ...e corresponding port direction registers are programmed The general purpose I O signals are configured as three ports each having up to 16 signals These three general purpose I O ports are shared with...

Page 396: ...al data bus mode is selected at reset by the input level on QSPI_DOUT WSEL The port D control register is used to configure pins that have multiple functions 0b01 through 0b11 but no GPIO function CAU...

Page 397: ...Field PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x0080 Figure 17 1 Port A Control Register PACNT Table 17 3 PACNT Field Descriptions Bi...

Page 398: ...17 16 PACNT8 Configure pin J2 00 PA8 01 FSC0 FSR0 1x Reserved 15 14 PACNT7 Configure pin P1 00 PA7 01 QSPI_CS3 10 DOUT3 11 Reserved 13 12 PACNT6 Configure pin E1 00 PA6 01 USB_RxD 1x Reserved 11 10 P...

Page 399: ...NT xx 11 Function 0b11 D2 PA0 USB_TP D1 PA1 USB_RP E5 PA2 USB_RN E4 PA3 USB_TN E3 PA4 USB_Susp E2 PA5 USB_TxEN E1 PA6 USB_RxD P1 PA7 QSPI_CS3 DOUT3 J2 PA8 FSC0 FSR0 J3 PA9 DGNT0 K5 PA10 DREQ0 L1 PA11...

Page 400: ...pin M9 00 PB13 01 E_RxD1 1x Reserved 25 24 PBCNT12 Configure pin N9 00 PB12 01 E_RxD2 1x Reserved 23 22 PBCNT11 Configure pin P9 00 PB11 01 E_RxD3 10 Reserved 11 Reserved 21 20 PBCNT10 Configure pin L...

Page 401: ...H1 The signal URT0_RxD is always internally connected to TIN2 00 PB1 01 URT0_RxD TIN2 1x Reserved 1 0 PBCNT0 Configure pin H4 00 PB0 01 URT0_TxD 1x Reserved Table 17 6 Port B Control Register Function...

Page 402: ...Port D has no data register nor data direction register Table 17 7 describes PDCNT fields Table 17 8 provides the same information organized by function 31 16 Field Reset R W 15 14 13 12 11 10 9 8 7...

Page 403: ...impedance 01 DIN0 10 URT1_RxD TIN3 11 Reserved 1 0 PDCNT0 Configure pin J4 00 High impedance 01 DCL0 10 URT1_CLK 11 Reserved Table 17 8 Port D Control Register Function Bits PIN Number PDCNTxx 00 Func...

Page 404: ...ten any internal pullups on the corresponding I O pins are disabled A detailed description is provided only for data direction register A PADDR The control bits in all three registers operate in the s...

Page 405: ...o setting the pin direction The reset values given in the following register diagrams are the port output values written to the registers during reset and do not reflect the value of a register read c...

Page 406: ...General Purpose I O Module MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 17 12 Freescale Semiconductor...

Page 407: ...lock diagram programming model and timing diagram 18 1 Overview The PWM module shown in Figure 18 1 generates a synchronous series of pulses having programmable duty cycle With a suitable low pass fil...

Page 408: ...that a new value can be loaded for the next cycle without affecting the current cycle At the beginning of each period the value of the width buffer register is loaded into the width register which fe...

Page 409: ...ns Bits Name Description 7 EN Enable 0 Disables the PWM While disabled the PWM is in low power mode and the prescaler does not count When the PWM is disabled the output is forced to the value of PWCRn...

Page 410: ...until after the counter has wrapped around The PWM must be disabled and then re enabled to affect its operation before the end of the current output cycle Figure 18 3 PWM Width Register PWWDn Figure 1...

Page 411: ...f each signal at reset The first listing is organized by function with signals appearing alphabetically within each functional group This is followed by a second listing sorted by pin number Some pins...

Page 412: ...SDWE A10_PRECHG DOUT0 URT1_TxD DIN0 URT1_RxD PA10_DREQ0 PA9 DGNT0 DCL0 URT1_CLK PA8 FSC0 FSR0 URT1_RTS INT5 URT1_CTS QSPI_CS2 DOUT1 DIN1 PA14 DREQ1 PA15_INT6 DGNT1_INT6 DCL1 GDCL1_OUT FSC1 FSR1 DFSC1...

Page 413: ...ee notes 1 Pin Functions Description Map BGA Pin I O Drive mA Cpf 0 Reset 1 2 3 A0 A0 D10 O 6 30 A1 SDA0 A1 SDRAM 16bit A0 B12 O 6 30 A10 SDA9 SDA8 A10 SDRAM 16bit A9 SDRAM 32bit A8 D12 O 6 30 A10_PRE...

Page 414: ...elect 3 N11 O 6 30 CS4 Chip select 4 M11 O 6 30 CS5 Chip select 5 L11 O 6 30 CS6 Chip select 6 P12 O 6 30 WSEL pin2 D0 PC0 D0 port C bit 0 L12 I O 6 30 WSEL pin2 D1 PC1 D1 port C bit 1 L13 I O 6 30 WS...

Page 415: ...C bit 4 K12 I O 6 30 WSEL pin2 D5 PC5 D5 port C bit 5 K13 I O 6 30 WSEL pin2 D6 PC6 D6 port C bit 6 K14 I O 6 30 WSEL pin2 D7 PC7 D7 port C bit 7 J11 I O 6 30 WSEL pin2 D8 PC8 D8 port C bit 8 J12 I O...

Page 416: ...k J4 I Port D Cntl Reg3 High Z DIN0 URT1_RxD IDL GCI data in UART1 Rx data K1 I Port D Cntl Reg3 High Z URT1_ CTS QSPI_ CS2 UART1 CTS QSPI_CS2 K2 I O 2 30 Port D Cntl Reg3 High Z URT1_RTS INT5 UART1 R...

Page 417: ...it 15 PLIC port 1 D channel grant Interrupt 6 input M3 I O 2 30 Port A Cntl Reg3 PA2 USB_RN Port A bit 2 USB Rx negative E5 I O 2 30 Port A Cntl Reg3 PA3 USB_TN Port A bit 3 USB Tx negative E4 I O 2 3...

Page 418: ...O 2 30 Port B Cntl Reg3 PB2 URT0_ CTS Port B bit 2 UART0 CTS H2 I O 2 30 Port B Cntl Reg3 PB3 URT0_ RTS Port B bit 3 UART0 RTS H3 I O 4 30 Port B Cntl Reg3 PB4 URT0_CLK Port B bit 4 UART0 baud clock...

Page 419: ...ect J14 O 10 30 SDBA1 SDRAM bank 1 select H12 O 10 30 SDCLK SDRAM bus clock Same frequency as CPU clock E14 O 10 30 SDCLKE SDRAM clock enable D13 O 10 30 SDCS CS7 SDRAM chip select CS7 B10 O 10 30 SDW...

Page 420: ...ot reconfigurable and has only one definition 2 WSEL BUSW1 BUSW0 HIZ and others refers to function determined by pull up or pull down value as seen by these address pins during reset 3 Port x Cntl Reg...

Page 421: ...6 D22 D6 D22 D6 I O A9 BS0 BS0 Byte strobe 0 O A10 RAS0 RAS0 SDRAM row select strobe O A11 A13 SDA12 SDA11 A13 SDA12 SDA11 A13 SDRAM 16bit A12 SDRAM 32bit A11 O A12 A2 SDA1 SDA0 A2 SDA1 SDA0 A2 SDRAM...

Page 422: ...AS0 SDRAM column select strobe O C10 A14 SDA13 SDA12 A14 SDA13 SDA12 A14 SDRAM 16bit A13 SDRAM 32bit A12 O C11 A11 SDA9 A11 SDA9 A11 SDRAM 32bit A9 O C12 A7 SDA6 SDA5 A7 SDA6 SDA5 A7 SDRAM 16bit A6 SD...

Page 423: ...SB driver I O E4 PA3 USB_TN PA3 USB_TN Port A bit 3 USB Tx negative I O E5 PA2 USB_RN PA2 USB_RN Port A bit 2 USB Rx negative I O E6 TEST TEST Device test mode enable I E7 GND Ground GND E8 GND Ground...

Page 424: ...B6 PB6 Port B bit 6 I O G5 VDD 3 3V VDD G6 GND Ground GND G7 GND Ground GND G8 GND Ground GND G9 GND Ground GND G10 VDD 3 3V VDD G11 D11 PC11 D11 PC11 D11 port C bit 11 I O G12 D27 D11 D27 D11 D27 D11...

Page 425: ...DD J7 GND Ground GND J8 GND Ground GND J9 VDD 3 3V VDD J10 VDD 3 3V VDD J11 D7 PC7 D7 PC7 D7 port C bit 7 I O J12 D8 PC8 D8 PC8 D8 port C bit 8 I O J13 D9 PC9 D9 PC9 D9 port C bit 9 I O J14 SDBA0 SDBA...

Page 426: ...al clock CS0 bus width bit 1 O L6 TIN0 TIN0 Timer 0 input I L7 E_Tx CLK E_Tx CLK Ethernet Tx clock I L8 PB10 E_TxD1 PB10 E_TxD1 Port B bit 10 Tx data bit 1 100 Base T Ethernet only I O L9 PB14 E_RxER...

Page 427: ...ip select 4 O M12 RSTI RSTI Device reset I M13 BYPASS BYPASS Bypass internal test mode O M14 CLKIN CLKIN CPU external clock input I N1 DOUT1 DOUT1 PLIC ports 1 2 3 data output O N2 DIN1 DIN1 PLIC port...

Page 428: ...QSPI_Din QSPI_Din QSPI data input I P5 High Z PWM_ OUT1 TOUT1 PWM_OUT1 TOUT1 PWM output compare 1 Timer 1 output compare O P6 E_COL E_COL Collision I P7 E_RxD0 E_RxD0 Ethernet Rx data I P8 E_TxEN E_T...

Page 429: ...figured for external 16 bit wide data bus and the data access is 32 bits wide the lower 16 bits of on chip data are not visible externally On chip cache ROM and SRAM accesses are not visible externall...

Page 430: ...g a read or write access BSn signals are asserted during accesses to on chip peripherals but not to on chip SRAM cache or ROM During SDRAM accesses these signals indicate a byte transfer between SDRAM...

Page 431: ...ternal SRAM when the decoded chip select is configured for either of the two SRAM ROM modes It is asserted during on chip peripherals accesses and negated during on chip SRAM accesses Table 19 4 Byte...

Page 432: ...low signal should never be applied to TA during such accesses For SDRAM accesses the bus cycle is terminated internally by circuitry in the SDRAM module 19 6 5 Hi Z HiZ is a test signal When it is con...

Page 433: ...a reset of the device is required without losing data located in SDRAM DRESETEN is normally tied high or low depending on system requirements It should never be tied to RSTI or RSTO 19 7 3 CPU Extern...

Page 434: ...PLIC TDM port 1 pins Port A general purpose I O PA 6 0 are multiplexed with USB module signals PA7 is multiplexed with QSPI_CS3 and DOUT3 Port B general purpose I O PB 4 0 are multiplexed with the UAR...

Page 435: ...d output from the UART0 module URT0_RTS can also be configured to be asserted and negated as a function of the RxFIFO level Port B mode This pin can also be configured as the PB3 I O 19 10 5 Clock URT...

Page 436: ...SB_RP Port A mode This pin can also be configured as the PA6 I O 19 11 8 USB_D and USB_D USB_D and USB_D are the on chip USB interface transceiver signals When these signals are enabled the USB module...

Page 437: ...de a trigger to the timer value capture logic 19 12 2 Timer Output TOUT0 PB7 Timer mode Timer output TOUT0 is the output from timer 0 Port B mode This pin can also be configured as I O pin PB7 19 12 3...

Page 438: ..._RxCLK input provides a timing reference for E_RxDV E_RxD 3 0 and E_RxER 19 13 6 Receive Data E_RxD0 E_RxD0 is the Ethernet input data transferred from the PHY to the media access controller when E_Rx...

Page 439: ...input after reset When the FEC is operated in 10Mbps 7 wire interface mode this signal should be connected to Vss 19 13 13 Transmit Error E_TxER Ethernet mode When the E_TxER output is asserted for on...

Page 440: ...ula in which n can be any value between 1 and 255 QSPI_CLK CLKIN 2 n At reset QSPI_CLK BUSW1 is used to configure the width of memory connected to CS0 BUSW1 configuration input is sampled on the risin...

Page 441: ...rt A mode This pin can be independently configured as PA8 19 16 1 2 D Channel Grant DGNT0 PA9 IDL mode This pin can be independently configured as the input DGNT0 used by a layer one ISDN S T transcei...

Page 442: ...ter serial data output for the UART1 module The output is held high mark condition when the transmitter is disabled idle or operating in the local loop back mode Data is shifted out least significant...

Page 443: ...used for clocking data into ports 2 and 3 19 16 2 4 GCI IDL Frame Sync FSC1 FSR1 DFSC1 IDL mode FSR1 is an input for the 8 KHz frame sync for port 1 GCI mode FSC1 is an input for the 8 KHz frame sync...

Page 444: ...to the port 1 data pins Port 2 uses the DFSC2 frame sync internally to ensure alignment with external devices synchronized with DFSC2 The width of this signal can be configured for 1 2 8 or 16 DCL clo...

Page 445: ...onfiguration register Note that the appropriate bits must be set in the pin configuration register to reassign this spin from the interrupt module to the PLIC module Interrupt mode This signal can be...

Page 446: ...fted in on the rising edge of TCK BDM mode DSI is the debug serial data input This signal requires a 10 K pullup resistor 19 17 5 JTAG TRST and BDM Data Clock TRST DSCLK JTAG mode TRST asynchronously...

Page 447: ...ave a pull down resistor The remaining three mode select signals must each have a 4 7 K pull up or pull down resistor These signals are sampled on the rising edge of Reset Output RSTO Table 19 7 Proce...

Page 448: ...d ground When the on chip USB transceiver is not used USB_GND should be connected to the device GND and USB_VDD left unconnected Refer to Section 12 2 1 1 USB Transceiver Interface Table 19 8 MCF5272...

Page 449: ...us master The MCF5272 does not support external bus masters The MCF5272 has three on chip bus masters the CPU the Ethernet controller and the memory to memory DMA controller 20 1 Features The followin...

Page 450: ...odes this signal is driven high NOTE Use the OE signal to control any external data bus transceivers In systems containing numerous external peripherals the chip selects should be used to qualify any...

Page 451: ...bus cycle TEA has no affect during SDRAM accesses 20 3 Bus Exception Double Bus Fault When a bus error or an address error occurs during the exception processing sequence for a previous bus error a pr...

Page 452: ...eset When the external physical address bus size is configured for 16 bits the signals D 15 0 become general purpose I O port C The MCF5272 determines the port size for each transfer from the CSBRs at...

Page 453: ...izes The multiplexer takes the four bytes of the 32 bit bus and routes them to their required positions For example OP3 can be routed to D 7 0 as would be the normal case when interfacing to a 32 bit...

Page 454: ...RAM D 23 16 1 0 1 1 FLASH SRAM D 15 8 0 1 1 1 FLASH SRAM D 7 0 1 1 0 0 FLASH SRAM Word D 31 16 0 0 1 1 FLASH SRAM D 15 0 0 0 0 0 FLASH SRAM Longword D 31 0 1 1 1 0 SDRAM Byte D 7 0 1 1 0 1 SDRAM D 15...

Page 455: ...arts the cycle with A 1 0 set to 0x0 and reads the first word The address in then incremented to 0x2 and the second word is read The data for both word reads is taken from D 31 16 Bytes labeled X are...

Page 456: ...TA is used to terminate the bus cycle the bus cycle will have a minimum of one wait states Additional wait states can be added by delaying the assertion of TA Figure 20 3 Longword Read EBI 00 32 Bit P...

Page 457: ...e Semiconductor 20 9 Figure 20 4 Word Write EBI 00 16 32 Bit Port Internal Termination Figure 20 5 Longword Read with Address Setup EBI 00 32 Bit Port Internal Termination SDCLK A 22 0 D 31 0 OE R W C...

Page 458: ...Semiconductor Figure 20 6 Longword Write with Address Setup EBI 00 32 Bit Port Internal Termination Figure 20 7 Longword Read with Address Hold EBI 00 32 Bit Port Internal Termination SDCLK A 22 0 D...

Page 459: ...iconductor 20 11 Figure 20 8 Longword Write with Address Hold EBI 00 32 Bit Port Internal Termination Figure 20 9 Longword Read EBI 00 32 Bit Port Terminated by TA with One Wait State SDCLK A 22 0 D 3...

Page 460: ...ort this EBI mode The key difference between EBI 11 and EBI 00 is that BS 3 0 can be directly connected to the R W inputs of the 8 bit wide SRAM devices and the R W output from the MCF5272 can be left...

Page 461: ...5272 ColdFire Integrated Microprocessor User s Manual Rev 3 Freescale Semiconductor 20 13 Figure 20 11 Word Write EBI 11 16 32 Bit Port Internal Termination SDCLK A 22 0 D 31 0 OE R W CSn BS 1 0 BS 3...

Page 462: ...le Semiconductor Figure 20 12 Read with Address Setup EBI 11 32 Bit Port Internal Termination Figure 20 13 Longword Write with Address Setup EBI 11 32 Bit Port Internal Termination SDCLK A 22 0 D 31 0...

Page 463: ...miconductor 20 15 Figure 20 14 Read with Address Hold EBI 11 32 Bit Port Internal Termination Figure 20 15 Longword Write with Address Hold EBI 11 32 Bit Port Internal Termination SDCLK A 22 0 D 31 0...

Page 464: ...egrated Microprocessor User s Manual Rev 3 20 16 Freescale Semiconductor Figure 20 16 Longword Read with Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination SDCLK A 22 0 D 31 0 OE R...

Page 465: ...boundary and increments A0 if the accessed port size is smaller than 16 bits The MCF5272 uses line write transfers to access a 16 byte operand for MOVEM instructions and DMA transfers when appropriate...

Page 466: ...e operand is properly aligned at any address a word operand is misaligned at an odd address and a longword is misaligned at an address that is not evenly divisible by four However because operands can...

Page 467: ...st must be held constant for at least two consecutive CLK periods to be considered a valid input MCF5272 latches the interrupt and the interrupt controller responds as programmed The interrupt service...

Page 468: ...elect signal Clock 2 C2 During C2 the MCF5272 drives the data bus the byte strobes and R W Clock 3 C3 During C3 the selected device detects an error and asserts TEA At the end of C3 or Cx the MCF5272...

Page 469: ...rable to retain SDRAM data in the case of catastrophic system failure In a production system if may be preferable to tie DRESETEN low Master reset resets the entire MCF5272 including the SDRAM control...

Page 470: ...STI is recognized internally the MCF5272 asserts the reset out pin RSTO The RSTO pin is asserted as long as RSTI is asserted and remains asserted for 32 768 CLKIN cycles after RSTI is negated During t...

Page 471: ...recognition by a specific falling edge is required Figure 20 22 Normal Reset Timing The levels of the mode select inputs QSPI_Dout WSEL QSPI_CLK BUSW1 QSPI_CS0 BUSW0 and HiZ are sampled when RSTO nega...

Page 472: ...esetting internal registers as with a normal reset The RSTO pin simultaneously asserts for 32K clocks after the software watchdog timeout Figure 20 23 illustrates the timing of RSTO when asserted by a...

Page 473: ...l peripherals with the exception of the SIM chip select interrupt controller GPIO module and SDRAM controller are reset also The SDRAM controller is reset only when DRESETEN is tied low SCR SOFTRST is...

Page 474: ...Bus Operation MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 20 26 Freescale Semiconductor...

Page 475: ...evice s pins into one shift register The contents of this register can be found at the ColdFire website at http www freescale com Test logic implemented using static logic design is independent of the...

Page 476: ...ned by the IEEE 1149 1 standard TCK should be grounded if the JTAG port is not used and MTMOD is tied low TMS BKPT Test mode select This input controls test mode operations for on board test logic def...

Page 477: ...oller states refer to the IEEE 1149 1 document Figure 21 2 TAP Controller State Machine TDI DSI Test and debug data in Input provided for loading serial data port shift registers boundary scan bypass...

Page 478: ...7 Note that when bidirectional data bits are sampled bit data can be interpreted only after examining the I O control bit to determine pin direction Open drain bidirectional bits require separate inpu...

Page 479: ...nductor 21 5 Figure 21 4 Input Cell I Cell Observe only BC 4 Figure 21 5 Output Control Cell En Cell BC 4 MUX Update DR G1 1 EXTEST CLAMP HI Z 0 Otherwise I O direction To next cell Shift DR From last...

Page 480: ...21 6 Bidirectional Cell IO Cell BC 6 Figure 21 7 General Arrangement for Bidirectional Pins MUX Update DR G1 1 EXTEST CLAMP HI Z 0 Otherwise To next cell Shift DR From last cell Clock DR Data from sys...

Page 481: ...d control signals The snapshot occurs on the rising edge of TCK in the capture DR controller state The data can be observed by shifting it transparently through the boundary scan register Because ther...

Page 482: ...st avoid situations in which the MCF5272 output drivers are enabled into actively driven networks Overdriving the TDO driver when it is active is not recommended 21 7 Non IEEE 1149 1 Operation In non...

Page 483: ...3 BS2 BS3 SDCLK F USB_D USB_D PB5 TA RSTO VDD VDD GND GND VDD VDD D12 PC12 D24 D8 D25 D9 D26 D10 G USB_VDD USB_GND PB4 URT0_CLK PB6 VDD GND GND GND GND VDD D11 PC11 D27 D11 D28 D12 D29 D13 H PB1 URT0_...

Page 484: ...F5272 ColdFire Integrated Microprocessor User s Manual Rev 3 22 2 Freescale Semiconductor 22 2 Package Dimensions Figure 22 2 shows MCF5272 package dimensions Figure 22 2 196 MAPBGA Package Dimensions...

Page 485: ...ages and temperatures The ratings in Table 23 1 define maximum conditions to which the MCF5272 may be subjected without being damaged However the device cannot operate normally while exposed to these...

Page 486: ...aware that device junction temperatures can be significantly influenced by board layout and surrounding devices Conformance to the device junction temperature specification can be verified by physical...

Page 487: ...PA 15 0 PB 15 0 TIN 1 0 IRQ 6 1 CLK TEA PST 3 0 DDATA 3 0 RSTI DRESETEN TDI TCK HIZ MTMOD Iin 20 A HI Z three state leakage current GND VDD A 22 0 D 31 0 OE RD R W TDO DSO ITSI 20 Signal low input cur...

Page 488: ...4 2 mA 30 pF PB 10 8 4 mA 30 pF PB 15 11 2 mA 30 pF USB_D 1 USB_D 1 DOUT1 2 mA 30 pF FSC1 2 mA 30 pF DCL1 4 mA 30 pF URT2_CTS 2 mA 30 pF URT2_RTS 2 mA 30 pF URT2_TxD 2 mA 30 pF QSPI_Dout 4 mA 30 pF QS...

Page 489: ...timings Clock input and output timings listed in Table 23 6 are shown in Figure 23 1 Figure 23 1 Clock Input Timing Diagram Table 23 6 Clock Input and Output Timing Specifications Name Characteristic...

Page 490: ...AM control register is 0 0 66 MHz Unit Min Max Control Inputs B1a 2 2 RSTI TA TEA and INTx are synchronized internally The setup time must be met only if recognition is needed on a particular clock ed...

Page 491: ...le 23 7 are shown in Figure 23 2 Figure 23 2 General Input Timing Requirements Invalid Invalid SDCLK Output TSETUP THOLD Input Setup And Hold 1 5V trise 1 5 nS Vh VIH Vl VIL 1 5V 1 5V Valid tfall 1 5...

Page 492: ...me Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max Control Outputs B6a SDCLK to chip selects CS 6 0 v...

Page 493: ...write SRAM bus timings listed in Table 23 8 are shown in Figure 23 3 Figure 23 4 Figure 23 5 and Figure 23 6 Figure 23 3 Read Write SRAM Bus Timing SDCLK CSn A 22 0 OE R W BS 3 0 D 31 0 TA H H S0 S2...

Page 494: ...23 10 Freescale Semiconductor Figure 23 4 shows an SRAM bus cycle terminated by TA showing timings listed in Table 23 8 Figure 23 4 SRAM Bus Cycle Terminated by TA SDCLK CSn A 22 0 OE R W BS 3 0 TA H...

Page 495: ...3 Freescale Semiconductor 23 11 Figure 23 5 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 23 8 Figure 23 5 SRAM Bus Cycle Terminated by TEA SDCLK CSn A 22 0 OE R W BS 3 0...

Page 496: ...Semiconductor Figure 23 6 shows reset and mode Select HIZ configuration timing showing parameters listed in Table 23 8 Figure 23 6 Reset and Mode Select HIZ Configuration Timing RSTI Mode selects SDCL...

Page 497: ...M serial port AC timing for the values in Table 23 9 Figure 23 8 BDM Serial Port AC Timing Table 23 9 Debug AC Timing Specification Num Characteristic 0 66 MHz Units Min Max D1 PST 3 0 DDATA 3 0 to PS...

Page 498: ...ences to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max Control Inputs SD1 SDCLK to address output A 22 0 valid 13 0 nS SD2 SDCLK to address out...

Page 499: ...23 15 Figure 23 9 SDRAM Signal Timing SDCLK DATA IN READ SDCR DATA OUT WRITE SD1 RAS0 CAS0 SDADR 13 0 DQMx SD3 SD5 SD6 SD16 SD14 SD8 SD7 SD7 SD8 SDWE SD8 SD7 SDBA 1 0 SD7 SD4 DATA IN SD16 SD15 READ S...

Page 500: ...ldFire Integrated Microprocessor User s Manual Rev 3 23 16 Freescale Semiconductor Figure 23 10 shows SDRAM self refresh timings listed in Table 23 10 Figure 23 10 SDRAM Self Refresh Cycle Timing SDCL...

Page 501: ...t In addition the processor clock frequency must exceed twice the E_RxCLK frequency Table 23 11 lists MII receive channel timings Figure 23 11 shows MII receive signal timings listed in Table 23 11 Fi...

Page 502: ...ising or falling edge of E_TxCLK and the timing is the same in either case This options allows the use of non compliant MII PHYs Refer to the Ethernet chapter for details of this option and how to ena...

Page 503: ...e 23 13 lists MII asynchronous inputs signal timing Figure 23 13 shows MII asynchronous input timings listed in Table 23 13 Figure 23 13 MII Async Inputs Timing Diagram Table 23 13 MII Async Inputs Si...

Page 504: ...annel timings listed in Table 23 14 Figure 23 14 MII Serial Management Channel Timing Diagram Table 23 14 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MDC falling edge to M...

Page 505: ...d in Table 23 15 Figure 23 15 Timer Timing Table 23 15 Timer Module AC Timing Specifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM...

Page 506: ...Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max UT1 URTnRxD valid to SDCLK setup 6 nS UT2 SDCLK to UR...

Page 507: ...rising edge of DFSC 3 1 20 nS P3 Delay from rising edge of GDCL1_OUT to DFSC 3 1 Invalid output Hold 2 nS P4 3 2 3 GDCL1_OUT must be less than 1 20th of the CPU operating frequency This is to ensure...

Page 508: ...id hold time 25 nS P16b DCL1 to FSR1 or FSC1 input Invalid hold time 25 nS P17a Delay from rising edge of DCL0 to low z and valid data on DOUT0 30 nS P17b Delay from rising edge of DCL1 to low z and v...

Page 509: ...L0 DCL1 pulse width low 45 55 of DCL period P35 DCL0 DCL1 pulse width high 45 55 of DCL period P38 Delay from rising edge of FSC0 to low z and valid data on DOUT0 Delay from rising edge of FSC1 to low...

Page 510: ...t be less than 1 20th of the CPU operating frequency to ensure minimum jitter to CODECs connected to Ports 1 2 3 3 Same as DCL0 and FSC0 if internal clock generator configured for pass through mode GD...

Page 511: ...d Microprocessor User s Manual Rev 3 Freescale Semiconductor 23 27 Figure 23 20 shows GCI master timings listed in Table 23 20 Figure 23 20 GCI Master Mode Timing DFSC1 GDCL1_OUT P59 P58 P57 P50 P51 D...

Page 512: ...23 21 General Purpose I O Port Timing Table 23 21 General Purpose I O Port AC Timing Specifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of th...

Page 513: ...of operation 1 1 USB_CLK accuracy should be 500ppm or better USB_CLK may be stopped to conserve power 48 48 MHz US2 2 2 Specification values are not tested USB_CLK fall time from Vh 2 4V to Vl 0 5V 2...

Page 514: ...a TCK fall time from Vh 2 4 V to Vl 0 5 V 5 nS J3b TCK rise time from Vl 0 5 V to Vh 2 4 V 5 nS J4 TDI TMS to TCK rising setup 10 nS J5 TCK rising edge to TDI TMS invalid hold 15 nS J6 Boundary scan d...

Page 515: ...23 24 QSPI Timing Table 23 24 QSPI Modules AC Timing Specifications Name Characteristic 0 66 MHz Unit Min Max QS1 QSPI_CS 3 0 to QSPI_CLK 1T1 1 T is defined as clock period in nS See Table 23 6 127T1...

Page 516: ...correspond to Figure 23 25 Figure 23 25 PWM Timing Table 23 25 PWM Modules AC Timing Specifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of th...

Page 517: ...ven register Absolute address MBAR register offset A 1 List of Memory Map Tables Table A 1 On Chip Module Base Address Offsets from MBAR Module Module Base Address Mnemonic Configuration Registers MBA...

Page 518: ...Debug only RCREG WCREG 0x0C00 ROMBAR 32 ROM Base Address Register MOVEC RCREG WCREG 0x0C04 RAMBAR 32 SRAM Base Address Register MOVEC RCREG WCREG 0x0C0F MBAR 32 Module Base Address Register MOVEC Tab...

Page 519: ...ption Register 4 CSOR4 0x0068 CS Base Register 5 CSBR5 0x006C CS Option Register 5 CSOR5 0x0070 CS Base Register 6 CSBR6 0x0074 CS Option Register 6 CSOR6 0x0078 CS Base Register 7 CSBR7 0x007C CS Opt...

Page 520: ...DR Reserved Table A 8 PWM Module Memory Map MBAR Offset 31 24 23 16 15 8 7 0 0x00C0 PWM Control Register 1 PWCR1 Reserved 0x00C4 PWM Control Register 2 PWCR2 Reserved 0x00C8 PWM Control Register 3 PWC...

Page 521: ...xiliary Control Register U0ACR Reserved 0x0114 UART0 Interrupt Status Register U0ISR Reserved 0x0114 UART0 Interrupt Mask Register U0IMR Reserved 0x0118 UART0 Baud Prescaler MSB U0BG1 Reserved 0x011C...

Page 522: ...xiliary Control Register U1ACR Reserved 0x0154 UART1 Interrupt Status Register U1ISR Reserved 0x0154 UART1 Interrupt Mask Register U1IMR Reserved 0x0158 UART1 Baud Prescaler MSB U1BG1 Reserved 0x015C...

Page 523: ...Reference Register TRR1 Reserved 0x0228 Timer 1 Capture Register TCAP1 Reserved 0x022C Timer 1 Counter Register TCN1 Reserved 0x0230 Timer 1 Event Register TER1 Reserved 0x0240 Timer 2 Mode Register T...

Page 524: ...Transmit P2DTR Port 3 D Data Transmit P3DTR 0x0350 Port0 GCI IDL Configuration Register P0CR Port1 GCI IDL Configuration Register P1CR 0x0354 Port2 GCI IDL Configuration Register P2CR Port3 GCI IDL Co...

Page 525: ...850 Ethernet Rx Ring Updated Flag RDAR 0x0854 Ethernet Tx Ring Updated Flag TDAR 0x0880 Ethernet MII Data Register MMFR 0x0884 Ethernet MII Speed Register MSCR 0x08CC Ethernet Receive Bound Register F...

Page 526: ...x103C USB Endpoint 4 Configuration Register EP4CFG 0x1040 USB Endpoint 5 Configuration Register EP5CFG 0x1044 USB Endpoint 6 Configuration Register EP6CFG 0x1048 USB Endpoint 7 Configuration Register...

Page 527: ...Register EP1DR 0x10B4 USB Endpoint 2 Data Register EP2DR 0x10B8 USB Endpoint 3 Data Register EP3DR 0x10BC USB Endpoint 4 Data Register EP4DR 0x10C0 USB Endpoint 5 Data Register EP5DR 0x10C4 USB Endpoi...

Page 528: ...List of Memory Maps MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 A 12 Freescale Semiconductor...

Page 529: ...s at higher clock speeds Minimize capacitive loading on signals to SDRAMs Operation of MCF5272 at highest frequencies i e 66MHz requires clean signals to ensure setup and hold times are met and to min...

Page 530: ...rmination R4 R1 R1 R1 R1 RA1 RA2 R2 RA5 RA3 RA4 RA6 RA7 RA8 RA9 RA10 RA3 SDRAM Flash D31 D0 Device D31 D0 1 Device D31 D0 2 Device D31 D0 3 CS0 CS1 CS2 CS3 32 OE CS0 CS1 CS2 CS3 D31 D0 Signals M CF527...

Page 531: ...R W 20 2 reset operation 20 21 sizing 20 4 soft reset operation 20 25 software watchdog timer reset operation 20 24 transfer acknowledge TA 20 2 transfer error acknowledge TEA 20 3 Byte strobes 20 8...

Page 532: ...llision handling 11 8 control register 11 11 descriptor active register 11 15 descriptor ring register pointer to receive 11 30 pointer to transmit 11 31 error handling 11 9 FEC initialization 11 34 F...

Page 533: ...terrupts bus acknowledge cycles 20 19 PLIC GCI 13 10 request inputs 19 23 J JTAG BDM debug port 21 2 boundary scan register 21 4 IDCODE register 6 11 instruction register 21 7 overview 21 1 restrictio...

Page 534: ...13 7 D Channel request register 13 32 D Channel status register 13 31 frame sync synthesis 13 13 GCI C I channel receive registers 13 28 transmit registers 13 29 transmit status register 13 30 GCI int...

Page 535: ...te low power 6 10 address 2 5 address A0 A6 2 5 ALPR 6 10 B2 data transmit 13 17 BI data receive 13 15 cache configuration 2 9 cache control 4 12 CACR 2 9 CCR 2 6 chip select base 8 3 general 8 2 opti...

Page 536: ...s 13 31 GCI C I channel receive 13 28 transmit 13 29 GCI monitor channel general 13 24 transmit 13 25 transmit status 13 27 general 13 15 interrupt configuration 13 20 loopback control 13 20 memory ma...

Page 537: ...CR 9 12 SDRAM auto initialization 9 9 banks page hits page misses 9 6 configuration register 9 6 controller signals 9 1 devices interface 9 4 interface 9 14 performance 9 10 power down and self refres...

Page 538: ...0 Transmit signal timing 23 18 U UART modules bus operation interrupt acknowledge cycles 16 29 read cycles 16 29 write cycles 16 29 clock source baud rates 16 20 external clock 16 21 FIFO stack in UAR...

Page 539: ...s 12 36 register access 12 30 descriptions 12 9 12 28 remote wakeup and resume operation 12 35 request processor 12 5 software architecture and application notes 12 31 transceiver interface 12 3 User...

Page 540: ...Index MCF5272 ColdFire Integrated Microprocessor User s Manual Rev 3 Index 10 Freescale Semiconductor...

Page 541: ...B Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus...

Page 542: ...B Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus...

Page 543: ...blank...

Page 544: ...o make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose...

Page 545: ...ibutor Click to View Pricing Inventory Delivery Lifecycle Information NXP MCF5272VM66 MCF5272CVM66 MCF5272CVF66 MCF5272VF66 MCF5272VF66R2 MCF5272VM66R2 MCF5272CVF66J MCF5272CVM66J MCF5272VF66J MCF5272...

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