NXP Semiconductors MCF5253, Reference Manual, Page: 630 / 648

FlexCAN Module
MCF5253 Reference Manual, Rev. 1
25-14 Freescale Semiconductor
• If the RXECTR increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to error-active state.
25.5.6 FlexCAN Error and Status Register (ERRSTATn)
ERRSTAT n reflects various error conditions, some general status of the device, and is the source of three
interrupts to the CPU. The reported error conditions (bits 15:10) are those occurred since the last time the
CPU read this register. The read action clears bits 15-10. Bits 9–3 are status bits.
Most bits in this register are read only, except for BOFFINT, WAKINT, and ERRINT, which are interrupt
flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to
Section 25.7.1, “Interrupts.”
Offset MBAR2 0x101C (ERRCNT0)
MBAR2 0x201C (ERRCNT1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXECTR TXECTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-8. FlexCAN Error Counter (ERRCNTn) Register
Table 25-7. FlexCAN Error Counter (ERRCNTn) Register Field Descriptions
Field Description
31–16 Reserved, should be cleared.
15–8
RXECTR
Receive error counter. Indicates current number of receive errors.
7–0
TXECTR
Transmit error counter. Indicates current number of transmit errors.
Offset MBAR2 0x1020 (CANCTRL0)
MBAR2 0x2020 (CANCTRL1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BIT1
ERR
BIT0
ERR ACK
ERR
CRC
ERR FRM
ERR STF
ERR
TX
WRN
RX
WRN
IDLE TXRX
FLT
CONF
0
BOFF
INT
ERR
INT
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-9. FlexCAN Error and Status (ERRSTATn) Register