NXP Semiconductors MCF5253, Reference Manual, Page: 629 / 648

FlexCAN Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 25-13
25.5.5 FlexCAN Error Counter Register (ERRCNTn)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: transmit error counter
(TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing these counters
are described in the CAN protocol and are completely implemented in the FlexCAN module. Both
counters are read-only, except in freeze mode, where they can be written by the CPU.
Writing to the ERRCNT n register while in freeze mode is an indirect operation. The data is first written to
an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit error-active or error-passive
flag, delay its transmission start time (error-passive), and avoid any influence on the bus when in bus off
state. The following are the basic rules for FlexCAN bus state transitions:
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the error and status register (ERRSTAT
n ) is updated to reflect error-passive state.
• If the FlexCAN state is error-passive, and either TXECTR or RXECTR decrements to a value less
than or equal to 127 while the other already satisfies this condition, the ERRSTAT
n [FLTCONF]
field is updated to reflect error-active state.
• If the value of TXECTR increases to be greater than 255, the ERRSTAT n [FLTCONF] field is
updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset
to zero.
• If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal counter to
count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset
to zero and counts in a manner where the internal counter counts 11 such bits and then wraps
around while incrementing the TXECTR. When TXECTR reaches the value of 128, the
ERRSTAT
n [FLTCONF] field is updated to be error-active, and both error counters are reset to
zero. At any instance of a dominant bit following a stream of less than 11 consecutive recessive
bits, the internal counter resets itself to zero without affecting the TXECTR value.
• If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ERRSTAT
n [ACKERR]
bit). After the transition to error-passive state, the TXECTR does not increment anymore by
acknowledge errors. Therefore, the device never goes to the bus off state.
Table 25-6. FlexCAN Rx Mask (RXGMASKn, RX14MASKn, RX15MASKn) Registers Field Descriptions
Field Description
31–29 Reserved, should be cleared.
28–18
MI28–18
Standard ID mask bits. These bits are the same mask bits for the Standard and Extended Formats.
17–0
MI17–0
Extended ID mask bits. These bits are used to mask comparison only in Extended Format.