Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-148
Freescale Semiconductor
24.12 Deviations from the EHCI Specifications
The host mode operation of the modules is nearly EHCI-compatible with few minor differences. For the
most part, the modules conform to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
•
Embedded Transaction Translator —Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
•
Device operation —In host mode, the device operational registers are generally disabled and thus
device mode is mostly transparent. However, there are a couple exceptions and they are
documented in the following sections.
•
Embedded design interface—The USB module does not have a PCI Interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
For the purposes of the USB OTG implementing dual-role host/device controller with support for OTG
applications, it is necessary to deviate from the EHCI specification. Device operation and OTG operation
are not specified in the EHCI and thus the implementation supported in the USB OTG module is
proprietary.
24.12.1 Embedded Transaction Translator Function
In Host mode, the USB module supports directly connected full and low speed devices without requiring
a companion controller, by including the capabilities of a USB 2.0 high speed hub transaction translator.
Although there is no separate Transaction Translator block in the system, the transaction translator
function normally associated with a high speed hub has been implemented within the DMA and Protocol
engine blocks. The embedded transaction translator function is an extension to EHCI interface, but makes
use of the standard data structures and operational models that exist in the EHCI specification to support
full and low speed devices.
24.12.1.1 Capability Registers
The following additions have been added to the capability registers to support the embedded Transaction
Translator Function:
•
N_TT added to HCSPARAMS
—
Host Controller Structural Parameters
•
N_PTT added to HSCPARAMS
—
Host Controller Structural Parameters
Section 24.6.2.3, “Host Controller Structural Parameters (HCSPARAMS)”
for usage information.
24.12.1.2 Operational Registers
The addition of two-bit Port Speed (PSPD) to the PORTSCn register is added to the operational registers
to support the embedded TT:
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...