NXP Semiconductors MCF5253, Reference Manual, Page: 487 / 648

Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 24-25
24.6.3.9 Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
This register is not defined in the EHCI specification. For the module in device mode, this register contains
the address of the top of the endpoint list in system memory. Bits [10–0] of this register cannot be modified
by the system software and always return zeros when read. The memory structure referenced by this
physical memory pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure, but
must be aligned on 64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a granularity
of 2 Kbytes, so in practice the queue head should be 2-Kbyte aligned.
This register is shared between the host and device mode functions. In device mode, it is the
ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See
Section 24.6.3.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),” for more
information.
Address MBAR2 0x758 (Host Mode) Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ASYBASE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ASYBASE(con’t)
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-20. Current Asynchronous List Address (ASYNCLISTADDR) Register
Table 24-22. Current Asynchronous List Address (ASYNCLISTADDR) Register Field Descriptions
Field Description
31–5
ASYBASE
Link Pointer Low (LPL). These bits correspond to memory address signal [31:5]. This field may reference only a
Queue Head (QH). Used only by the host controller.
4–0 Reserved.