NXP Semiconductors MCF5253, Reference Manual, Page: 461 / 648

Advanced Technology Attachment Controller (ATA)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 23-35
NOTE
There may be less than <packetsize> remaining bytes, so transfer will not
be automatic by the DMA.
23.6.5 Using DMA Mode to Transmit Data to ATA Bus
Apart from PIO mode, the ATA interface supports also MDMA and UDMA mode to transfer data. DMA
mode can be used to transmit data to the drive (DMA out transfer). In DMA transmit mode, the protocol
engine will transfer data from the FIFO to the drive using multiword DMA or ultra DMA protocol. The
transfer will pause when one of following occurs:
• The FIFO is empty.
• The drive deasserts its dma request signal ATA_DMARQ.
• The bit dma_pending in the ata_contol register is cleared.
When the cause of the transfer pausing is removed, the transfer restarts. The end of the transfer is signalled
by the drive to the host by asserting the ATA_INTRQ signal. Alternatively, the host can read the device
status register. In this register, the drive will also indicate if the transfer has ended.
The transfer of data from the memory to the FIFO is handled by the host system DMA. Whenever the FIFO
filling is below the alarm threshold, the DMA should read one packet of data from the main memory, and
store this in the FIFO. In doing so, the DMA prevents the FIFO from getting empty, and keeps the transfer
from FIFO to drive running.
The steps for setting up a DMA data transfer from device to host are:
1. Make sure the ATA bus is not in reset and all timing registers are programmed.
2. Make sure the FIFO is empty by reading it until empty, or by resetting it.
3. Initialize the DMA channel connected to fifo_tx_alarm. Every time fifo_tx_alarm is high, the
DMA should read <packetsize> long ints from the main memory, and write them to the FIFO.
(typical packetsize is 8 longs). Program the DMA such that it will not transfer more than
<sectorsize> longwords in total.
4. Write FIFO_SIZE - 2 * <packetsize> to fifo_alarm register. In this way, FIFO will request attention
to DMA when there is room for at least one extra packet. FIFO_SIZE should be given in halfwords.
(typical 64 halfwords)
5. To make the ATA ready for a DMA transfer from host to device, perform the following steps:
a) Make sure the FIFO is out of reset by setting bit fifo_rst_b to 1 in the ata control register.
b) Program fifo_tx_en=1 in ata_control register. This enables the FIFO to be filled by DMA.
c) Program dma_pending=1, dma_write=1, ultra_mode_selected=0/1 in ata_control register.
ultra_mode_selected should be 1 if you want to transfer data using UDMA mode, it should be
0 if you want to transfer data using MDMA mode.
6. Now, the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to
request DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this
document. You should consult the ATA specification to know how to communicate with the drive.