NXP Semiconductors MCF5253, Reference Manual, Page: 413 / 648

IEEE 1149.1 Test Access Port (JTAG)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 21-3
21.3.1 Test Clock (TCK)
TCK is the dedicated JTAG test logic clock that is independent of the MCF5253 processor clock. Various
JTAG operations occur on the rising or falling edge of TCK. The internal JTAG controller logic is designed
such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to
lose state information. If TCK is not used, it should be tied to Vdd. There is an internal pullup connected
to this pin.
21.3.2 Test Reset/Development Serial Clock (TRST/DSCLK)
The TEST[2:0] signals determine the function of this dual-purpose pin. If TEST[2:0]=001, the DSCLK
function is selected. If TEST[2:0]= 000, the TRST function is selected, the pin has an internal pullup and
the JTAG reset is executed. For all other modes the signal is forced internally to its active value. TEST[2:0]
should not be changed while RSTI is asserted.
When used as TRST, this pin asynchronously resets the internal JTAG controller to the test logic reset
state, causing the JTAG instruction register to choose the “idcode” command. When this occurs, all the
JTAG logic is benign and will not interfere with the normal functionality of the MCF5253 processor.
Although this signal is asynchronous, Freescale recommends that TRST make only a 0 to 1 (asserted to
negated) transition while TMS is held at a logic 1 value. TRST has an internal pullup so that if it is not
driven low its value will default to a logic level of 1. However, if TRST is not used, it can either be tied to
ground or, if TCK is clocked, it can be tied to VDD. The former connection will place the JTAG controller
in the test logic reset state immediately, while the later connection will cause the JTAG controller (if TMS
is a logic 1) to eventually end up in the test logic reset state after 5 clocks of TCK.
This pin is also used as the development serial clock (DSCLK) for the serial interface to the debug
module.The maximum frequency for the DSCLK signal is 1/2 the SYSCLK frequency.
21.3.3 Test Mode Select/ Breakpoint (TMS/BKPT)
The TEST[2:0] signals determine this pin’s dual function. If TEST[2:0] =001, the BKPT function is
selected. If TEST[2:0] = 000, then the TMS function is selected. TEST[2:0] should not change while RSTI
is asserted. When used as TMS, this input signal provides the JTAG controller with information to
determine which test operation mode should be performed. The value of TMS and current state of the
internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG
controller holds its current state or advances to the next state. This directly controls whether JTAG data or
TDI A serial test data input with a default internal pullup resistor that is sampled on the rising
edge of TCK.
TDO A tri-state test data output that is actively driven only in the Shift-IR and Shift-DR controller
states and only updates on the falling edge of TCK.
TRST An active-low asynchronous reset with a default internal pullup resistor that forces the TAP
controller into the test-logic-reset state.
Table 21-1. JTAG Pin Descriptions
Pin Description