NXP Semiconductors MCF5253, Reference Manual, Page: 395 / 648

Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 20-25
DRc encoding:
Command Sequence:
Figure 20-26. Write Debug Module Register Command Sequence
Operand Data:
Longword data is written into the specified debug register. The data is supplied most significant word first.
Result Data:
Command complete status ($0FFFF) is returned when register write is complete.
20.3.4.1.13 Unassigned Opcodes
Unassigned command opcodes are reserved by Freescale. All unused command formats within any
revision level perform a NOP and return the ILLEGAL command response
.
20.3.4.2 BDM Accesses of the eMAC Registers
The presence of rounding logic in the output data path of the eMAC requires special care for
BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must
Table 20-16. Definition of DRc Encoding—Write
DRc[3:0] Debug Register Definition Mnemonic Initial State
$0 Configuration/Status CSR $0
$1-$4 Reserved – –
$5 BDM Address Attribute BAAR $5
$6 Bus Attributes and Mask AATR $5
$7 Trigger Definition TDR $0
$8 PC Breakpoint PBR –
$9 PC Breakpoint Mask PBMR –
$A-$B Reserved – –
$C Operand Address High Breakpoint ABHR –
$D Operand Address Low Breakpoint ABLR –
$E Data Breakpoint DBR –
$F Data Breakpoint Mask DBMR –
Next CMD
“Not Ready”
LS Data
“Illegal”
WDMREG
???
MS Data
XXX
Next CMD
“Cmd Complete”
“Not Ready”
“Not Ready”