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64 KByte Flash Module (S12FTMRG64K4KV2)
MC9S12VRP Family Reference Manual Rev. 1.3
478
NXP Semiconductors
). The Verify Backdoor Access Key command must not be executed from the Flash block
containing the backdoor comparison key to avoid code runaway.
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
18.4.6.12 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of the P-Flash or D-Flash block.
Table 18-52. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0C
Not required
001
Key 0
010
Key 1
011
Key 2
100
Key 3
Table 18-53. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
FSTAT
ACCERR
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Set if the backdoor key has mismatched since the last reset
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
Table 18-54. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0D
Flash block selection code [1:0]
.
See
001
Margin level setting.
Summary of Contents for MC9S12VRP64
Page 16: ...MC9S12VRP Family Reference Manual Rev 1 3 16 NXP Semiconductors ...
Page 46: ...Device Overview S12VRP Series MC9S12VRP Family Reference Manual Rev 1 3 46 NXP Semiconductors ...
Page 236: ...S12S Debug Module S12DBGV2 MC9S12VRP Family Reference Manual Rev 1 3 236 NXP Semiconductors ...
Page 244: ...Interrupt Module S12SINTV1 MC9S12VRP Family Reference Manual Rev 1 3 244 NXP Semiconductors ...
Page 358: ...Timer Module TIM16B2CV3 MC9S12VRP Family Reference Manual Rev 1 3 358 NXP Semiconductors ...
Page 436: ...Supply Voltage Sensor BATSV2 MC9S12VRP Family Reference Manual Rev 1 3 436 NXP Semiconductors ...
Page 528: ...NVM Electrical Parameters MC9S12VRP Family Reference Manual Rev 1 3 528 NXP Semiconductors ...
Page 530: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 530 NXP Semiconductors ...
Page 531: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 531 ...
Page 532: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 532 NXP Semiconductors ...