NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 224 / 555

S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
224 NXP Semiconductors
NOTE:
When tracing is terminated using forced breakpoints, latency in breakpoint
generation means that opcodes following the opcode causing the breakpoint
can be stored to the trace buffer. The number of opcodes is dependent on
program flow. This can be avoided by using tagged breakpoints.
6.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes)
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix
refers to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail
mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of
entries is 32. In this case DBGCNT bits are incremented twice, once for the address line and once for the
data line, on each trace buffer entry. In Detail mode CINF comprises of R/W and size access information
(CRW and CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
6.4.5.3.1 Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
Mode
Entry
Number
4-bits 8-bits 8-bits
Field 2 Field 1 Field 0
Detail Mode
Entry 1
CINF1,ADRH1 ADRM1 ADRL1
0 DATAH1 DATAL1
Entry 2
CINF2,ADRH2 ADRM2 ADRL2
0 DATAH2 DATAL2
Normal/Loop1
Modes
Entry 1 PCH1 PCM1 PCL1
Entry 2 PCH2 PCM2 PCL2
Bit 3 Bit 2 Bit 1 Bit 0
CSZ CRW ADDR[17] ADDR[16]
Figure 6-25. Field2 Bits in Detail Mode