S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
214
NXP Semiconductors
6.3.2.8.8
Debug Comparator Data Low Mask Register (DBGADLM)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
6.4
Functional Description
This section provides a complete functional description of the DBG module. If the part is in secure mode,
the DBG module can generate breakpoints but tracing is not possible.
6.4.1
S12DBGV2 Operation
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data
in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main
blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor
address bus activity. Comparator A can also be configured to monitor databus activity and mask out
individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte
access qualification in the comparison. A match with a comparator register value can initiate a state
sequencer transition to another state (see
). Either forced or tagged matches are possible. Using
Table 6-30. DBGADHM Field Descriptions
Field
Description
7–0
Bits[15:8]
Comparator Data High Mask Bits
— The Comparator data high mask bits control whether the selected
comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus
comparisons are only performed if the TAG bit in DBGACTL is clear
0 Do not compare corresponding data bit Any value of corresponding data bit allows match.
1 Compare corresponding data bit
Address: 0x002F
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 6-22. Debug Comparator Data Low Mask Register (DBGADLM)
Table 6-31. DBGADLM Field Descriptions
Field
Description
7–0
Bits[7:0]
Comparator Data Low Mask Bits
— The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus
comparisons are only performed if the TAG bit in DBGACTL is clear
0 Do not compare corresponding data bit. Any value of corresponding data bit allows match
1 Compare corresponding data bit
Summary of Contents for MC9S12VRP64
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Page 46: ...Device Overview S12VRP Series MC9S12VRP Family Reference Manual Rev 1 3 46 NXP Semiconductors ...
Page 236: ...S12S Debug Module S12DBGV2 MC9S12VRP Family Reference Manual Rev 1 3 236 NXP Semiconductors ...
Page 244: ...Interrupt Module S12SINTV1 MC9S12VRP Family Reference Manual Rev 1 3 244 NXP Semiconductors ...
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Page 436: ...Supply Voltage Sensor BATSV2 MC9S12VRP Family Reference Manual Rev 1 3 436 NXP Semiconductors ...
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