Analog-to-Digital Converter (S08ADC12V1)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors
137
10.4.4.2
Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 12-bit or 10-bit MODE (the ADCRH register has
been read but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO
is not set, and the new result is lost. In the case of single conversions with the compare function enabled
and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases
of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of
ADCO (single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
10.4.4.3
Aborting Conversions
Any conversion in progress is aborted when:
•
A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
•
A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
•
The MCU is reset.
•
The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.
However, they continue to be the values transferred after the completion of the last successful conversion.
If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
10.4.4.4
Power Control
The ADC module remains in its idle state until a conversion is initiated.
If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum
value for f
ADCK
(see the electrical specifications).
10.4.4.5
Sample Time and Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (
f
ADCK
).
After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5
ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
Summary of Contents for MC9S08QL4
Page 4: ...MC9S08QL8 MCU Series Reference Manual Rev 1 4 NXP Semiconductors...
Page 36: ...Chapter 3 Modes of Operation MC9S08QL8 MCU Series Reference Manual Rev 1 36 NXP Semiconductors...
Page 56: ...Chapter 4 Memory MC9S08QL8 MCU Series Reference Manual Rev 1 56 NXP Semiconductors...
Page 172: ...Modulo Timer S08MTIMV1 MC9S08QL8 MCU Series Reference Manual Rev 1 172 NXP Semiconductors...
Page 238: ...Development Support MC9S08QL8 MCU Series Reference Manual Rev 1 238 NXP Semiconductors...
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