NXP Semiconductors MC9S08LG16, Reference Manual

Page: 244 / 373

Chapter 10 Inter-Integrated Circuit (S08IICV2)
MC9S08LG32 MCU Series, Rev. 5
244 Freescale Semiconductor
Figure 12-2. IIC Functional Block Diagram
12.2 External Signal Description
This section describes each user-accessible pin signal.
12.2.1 SCL — Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
12.2.2 SDA — Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
12.3 Register Definition
This section consists of the IIC register descriptions in address order.
Refer to the direct-page register summary in Chapter 4, “Memory ,” for the absolute address assignments
for all IIC registers. This section refers to registers and control bits only by their names. A
Input
Sync
In/Out
Data
Shift
Register
Address
Compare
Interrupt
Clock
Control
Start
Stop
Arbitration
Control
CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG
ADDR_DECODE DATA_MUX
Data Bus
SCL
SDA
Address