NXP Semiconductors MC9S08LG16, Reference Manual

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MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 226
Chapter 11
Internal Clock Source (S08ICSV3)
11.1 Introduction
The internal clock source (ICS) module provides clock source choices for the MCU. The module contains
a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external
reference clock. The module can provide this FLL clock or either of the internal or external reference
clocks as a source for the MCU system clock. There are also signals provided to control a low-power
oscillator (XOSC) module to allow the use of an external crystal/resonator as the external reference clock.
Whichever clock source is chosen for ICSOUT, it is passed through a reduced bus divider (BDIV) which
allows a lower final output clock frequency to be derived.
NOTE
The ICS on the MC9S08LG32 series is configured to support only the low
and mid range DCO, therefore the DRS[1] and DRST[1] bits in ICSSC have
no effect. The FLL will only multiply the reference clock by 512/1024 or
608/1216 depending on the state of the DMX32 bit.
Figure 11-1 shows the MC9S08LG32 series block diagram with the ICS block highlighted.
During user modes, the trim registers of ICS are automatically loaded with factory programmed values.
During debug modes, the trim registers of ICS default to predefined values (see
Section 11.3.3, “ICS Trim
Register (ICSTRM) ” and Section 11.3.4, “ICS Status and Control (ICSSC) ”). To get trimmed clock values
in debug mode, the user can follow the steps as described in Section 4.4.1, “Reserved Flash Locations .”