NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 189
• LCDEN is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state.
• 1/4 duty
• 1/3 bias
• LCLK[2:0], VSUPPLY[1:0], CPSEL and BRATE[2:0] revert to their reset values
9.4.6 Interrupts
When an LCD module frame-frequency interrupt event occurs, the LCDIF bit in the LCDS register is
asserted. The LCDIF bit remains asserted until software clears the LCD-module-frame-frequency
interrupt. The interrupt can be cleared by software writing a 1 to the LCDIF bit.
If both the LCDIF bit in the LCDS register and the LCDIEN bit in the LCDC1 register are set, an LCD
interrupt signal asserts.
9.5 Initialization Section
This section provides a recommended initialization sequence for the LCD module and also includes
initialization examples for several LCD application scenarios.
9.5.1 Initialization Sequence
The below list provides a recommended initialization sequence for the LCD module.
You must write to all LCDPEN, LCDBPEN, and LCDWF registers to initialize their values after a reset.
1. LCDC0 register
a) Configure LCD clock source (SOURCE bit).
2. LCDSUPPLY register
a) Enable charge pump (CPSEL bit).
b) Configure charge pump clock (LADJ[1:0]).
c) Configure LCD power supply (VSUPPLY[1:0]).
3. LCDC1 register
a) Configure LCD frame frequency interrupt (LCDIEN bit).
b) Configure LCD behavior in low-power mode (LCDWAI and LCDSTP bits).
4. LCDC0 register
a) Configure LCD duty cycle (DUTY[2:0]).
b) Select and configure LCD frame frequency (LCLK[2:0]).
5. LCDBCTL register
a) Configure display mode (ALT and BLANK bits).
b) Configure blink mode (BMODE).
c) Configure blink frequency (BRATE[2:0]).