NXP Semiconductors MC9S08LG16, Reference Manual

Page: 186 / 373

Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
186 Freescale Semiconductor
Figure 9-16. LCD Charge Pump and Voltage Divider Block Diagram
NOTE:
The charge pump is optimized for 1/3 bias mode operation only.
During the first 16 timebase clock cycles after the LCDPEN bit is set, all the
LCD frontplane and backplane outputs are disabled, regardless of the state
of the LCDEN bit.
The charge pump requires external capacitance for its operation. To provide
this external capacitance, the V
cap1
and V
cap2
external pins are provided. It
is recommended that a ceramic capacitor be used. Proper orientation is
imperative when using a polarized capacitor. The recommended value for
the external capacitor is 0.1
μ
F.
9.4.4.1 LCD Charge Pump and Voltage Divider
Using the voltage divider and charge pump, the LCD module can be used to generate various voltages.
This LCD module configurability makes the LCD module compatible with both 3 V or 5 V LCD glass.
V
LL1
V
LL2
V
LL3
CHARGE PUMP
powersw1
powersw2
~CPSEL
VSUPPLY[1:0] Configuration powersw1 powersw2
00 Drive V
LL2
internally from V
DD
1 0
01 Drive V
LL3
internally from V
DD
0 1
10 Reserved 0 0
11 Drive V
LL3
externally from V
DD
0 0
V
DD
~CPSEL
~CPSEL