M68HC16 Z SERIES
REGISTER SUMMARY
USER’S MANUAL
D-49
DSCKL[6:0] — Delay before SCK
When the DSCK bit is set in a command RAM byte, this field determines the length of
the delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-
select pins. The following equation determines the actual delay before SCK:
where DSCKL[6:0] is in the range of one to 127.
When DSCK is zero in a command RAM byte, then DSCKL[6:0] is not used. Instead,
the PCS valid to SCK transition is one-half the SCK period.
DTL[7:0] — Length of Delay after Transfer
When the DT bit is set in a command RAM byte, this field determines the length of the
delay after a serial transfer. The following equation is used to calculate the delay:
where DTL is in the range of one to 255.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192
÷
f
sys
.
If DT is zero in a command RAM byte, a standard delay is inserted:
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. This is controlled by the DT bit in a command RAM byte.
D.6.12 QSPI Control Register 2
SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIFIE
WREN
WRTO
0
ENDQP[3:0]
0
0
0
0
NEWQP[3:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCS to SCK Delay
DSCKL[6:0]
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-------------------------------
=
Delay after Transfer
32
DTL[7:0]
×
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------------------------------------
=
Standard Delay after Transfer
17
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--------
=
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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