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NXP Semiconductors MC68CK16Z1, User Manual

The NXP Semiconductors MC68CK16Z1 product provides advanced integrated circuits for high-performance applications. For detailed instructions on how to maximize the potential of this product, download the free User Manual from manualshive.com. This comprehensive manual will guide you through the features and functionalities of the MC68CK16Z1.

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-8

USER’S MANUAL

Data transfer is synchronized with the internally-generated serial clock (SCK). Control
bits CPHA and CPOL in SPCR control clock phase and polarity. Combinations of
CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing
data from the MOSI pin and latches incoming data from the MISO pin.

10.3.3.2 Slave Mode

Clearing the MSTR bit in SPCR selects slave mode operation. In slave mode, the SPI
is unable to initiate serial transfers. Transfers are initiated by an external bus master.
Slave mode is typically used on a multimaster SPI bus. Only one device can be bus
master (operate in master mode) at any given time.

When using the SPI in slave mode, include the following steps:

1. Write to the MMCR and interrupt registers. Refer to

10.5 MCCI Initialization

for

more information.

2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and

SS. MISO is used for serial data output in slave mode, and MOSI is used for
serial data input. Either or both may be necessary, depending on the particular
application. SCK is the input serial clock. SS selects the SPI when asserted.

3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK,

MOSI, and SS pins as inputs. Configure MISO as an output.

4. Write to the SPCR to assign values for CPHA, CPOL, SIZE, LSBF, WOMP, and

SPIE. Set the MSTR bit to select master operation. Set the SPE bit to enable
the SPI. (The BAUD field in the SPCR of the slave device has no effect on SPI
operation.)

When SPE is set and MSTR is clear, a low state on the SS pin initiates slave mode
operation. The SS pin is used only as an input.

After a byte or word of data is transmitted, the SPI sets the SPIF flag. If the SPIE bit in
SPCR is set, an interrupt request is generated when SPIF is asserted.

Transfer is synchronized with the externally generated SCK. The CPHA and CPOL
bits determine the SCK edge on which the slave MCU latches incoming data from the
MOSI pin and drives outgoing data from the MISO pin.

10.3.4 SPI Clock Phase and Polarity Controls

Two bits in the SPCR determine SCK phase and polarity. The clock polarity (CPOL)
bit selects clock polarity (high true or low true clock). The clock phase control bit
(CPHA) selects one of two transfer formats and affects the timing of the transfer. The
clock phase and polarity should be the same for the master and slave devices. In some
cases, the phase and polarity may be changed between transfers to allow a master
device to communicate with slave devices with different requirements. The flexibility
of the SPI system allows it to be directly interfaced to almost any existing synchronous
serial peripheral.

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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Summary of Contents for MC68CK16Z1

Page 1: ...A G R E E M E N T R E Q U I R E D M68HC16Z Series MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 User s Manual HC16 HC16 HC16 Freescale Semiconductor I nc Freescale Semi...

Page 2: ...t or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or us...

Page 3: ...al Module QSM 3 2 3 1 7 Multichannel Communication Interface MCCI MC68HC16Z4 CKZ4 Only 3 2 3 1 8 General Purpose Timer GPT 3 2 3 2 Intermodule Bus 3 2 3 3 System Block Diagram and Pin Assignment Diagr...

Page 4: ...CPU Instruction Sets 4 31 4 9 Instruction Format 4 33 4 10 Execution Model 4 34 4 10 1 Microsequencer 4 35 4 10 2 Instruction Pipeline 4 35 4 10 3 Execution Unit 4 35 4 11 Execution Process 4 36 4 11...

Page 5: ...ration 5 3 5 3 System Clock 5 4 5 3 1 Clock Sources 5 5 5 3 2 Clock Synthesizer Operation 5 6 5 3 3 External Bus Clock 5 21 5 3 4 Low Power Operation 5 21 5 4 System Protection 5 24 5 4 1 Reset Status...

Page 6: ...Cycles 5 43 5 6 5 1 Bus Errors 5 44 5 6 5 2 Double Bus Faults 5 45 5 6 5 3 Halt Operation 5 45 5 6 6 External Bus Arbitration 5 46 5 6 6 1 Show Cycles 5 47 5 7 Reset 5 48 5 7 1 Reset Exception Process...

Page 7: ...gnals for Interrupt Acknowledge 5 68 5 9 4 Chip Select Reset Operation 5 69 5 10 Parallel Input Output Ports 5 70 5 10 1 Pin Assignment Registers 5 70 5 10 2 Data Direction Registers 5 70 5 10 3 Data...

Page 8: ...Status Registers 8 6 8 7 2 Clock and Prescaler Control 8 6 8 7 3 Sample Time 8 7 8 7 4 Resolution 8 7 8 7 5 Conversion Control Logic 8 7 8 7 5 1 Conversion Parameters 8 8 8 7 5 2 Conversion Modes 8 8...

Page 9: ...on 9 8 9 3 5 QSPI Operating Modes 9 9 9 3 5 1 Master Mode 9 16 9 3 5 2 Master Wrap Around Mode 9 19 9 3 5 3 Slave Mode 9 20 9 3 5 4 Slave Wrap Around Mode 9 21 9 3 6 Peripheral Chip Selects 9 21 9 4 S...

Page 10: ...y Controls 10 8 10 3 4 1 CPHA 0 Transfer Format 10 9 10 3 4 2 CPHA 1 Transfer Format 10 10 10 3 5 SPI Serial Clock Baud Rate 10 11 10 3 6 Wired OR Open Drain Outputs 10 11 10 3 7 Transfer Size and Dir...

Page 11: ...11 7 11 5 1 Input Capture Pins 11 7 11 5 2 Input Capture Output Compare Pin 11 7 11 5 3 Output Compare Pins 11 7 11 5 4 Pulse Accumulator Input Pin 11 7 11 5 5 Pulse Width Modulation 11 8 11 5 6 Auxi...

Page 12: ...atus Register D 8 D 2 5 System Integration Test Register E D 9 D 2 6 Port E Data Register D 9 D 2 7 Port E Data Direction Register D 9 D 2 8 Port E Pin Assignment Register D 10 D 2 9 Port F Data Regis...

Page 13: ...egister D 30 D 5 3 Port ADA Data Register D 30 D 5 4 ADC Control Register 0 D 31 D 5 5 ADC Control Register 1 D 32 D 5 6 ADC Status Register D 36 D 5 7 Right Justified Unsigned Result Register D 36 D...

Page 14: ...ister D 68 D 8 4 Port GP Data Direction Register Data Register D 69 D 8 5 OC1 Action Mask Register Data Register D 69 D 8 6 Timer Counter Register D 70 D 8 7 Pulse Accumulator Control Register Counter...

Page 15: ...ample 3 Changing Clock Frequencies E 16 E 2 1 4 Example 4 Software Watchdog Periodic Interrupt and Autovector Demo E 18 E 2 2 CPU16 Programming Example E 23 E 2 2 1 Example 5 Indexed and Extended Addr...

Page 16: ...M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 17: ...CKZ1 CMZ1 Separate Program and Data Space Map 3 23 3 15 MC68HC16Z2 Z3 Separate Program and Data Space Map 3 24 3 16 MC68HC16Z4 CKZ4 Separate Program and Data Space Map 3 25 4 1 CPU16 Register Model 4...

Page 18: ...Point of Power Supply Origin 8 17 8 7 Input Pin Subjected to Negative Stress 8 18 8 8 Voltage Limiting Diodes in a Negative Stress Circuit 8 19 8 9 External Multiplexing of Analog Signal Sources 8 20...

Page 19: ...Mode Select Timing Diagram A 36 A 13 Background Debug Mode Timing Diagram Serial Communication A 39 A 14 Background Debug Mode Timing Diagram Freeze Assertion A 39 A 15 ECLK Timing Diagram A 44 A 16...

Page 20: ...1 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 132 Pin Package B 2 B 2 MC68HC16Z4 CKZ4 Pin Assignments for 132 Pin Package B 3 B 3 Case 831A 01 132 Pin Package Dimensions B 4 B 4 MC68HC16Z1 CKZ1 CMZ...

Page 21: ...s 5 11 5 4 25 17 MHz Clock Control Multipliers 5 13 5 5 16 78 MHz System Clock Frequencies 5 15 5 6 System Clock Frequencies for a 20 97 MHz System 5 17 5 7 System Clock Frequencies for a 25 17 MHz Sy...

Page 22: ...Register Formats 8 14 8 10 External Circuit Settling Time 10 Bit Conversions 8 23 8 11 Error Resulting From Input Leakage IOFF 8 23 9 1 Effect of DDRQS on QSM Pin Function 9 4 9 2 QSPI Pins 9 8 9 3 Bi...

Page 23: ...g A 37 A 21 20 97 MHz Background Debug Mode Timing A 38 A 22 25 17 MHz Background Debug Mode Timing A 38 A 23 Low Voltage ECLK Bus Timing A 40 A 24 16 78 MHz ECLK Bus Timing A 41 A 25 20 97 MHz ECLK B...

Page 24: ...M Array Address Space Type D 23 D 21 MRM Address Map D 25 D 22 ROM Array Space Field D 26 D 23 Wait States Field D 26 D 24 ADC Module Address Map D 29 D 25 Freeze Encoding D 30 D 26 Sample Time Select...

Page 25: ...D 71 D 45 PACLK 1 0 Effects D 71 D 46 OM OL 5 2 Effects D 72 D 47 EDGE 4 1 Effects D 72 D 48 CPR 2 0 Prescaler Select Field D 73 D 49 PPR 2 0 Field D 75 D 50 PWM Frequency Ranges D 76 Freescale Semico...

Page 26: ...M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 27: ...An internal phase locked loop circuit synthesizes the sys tem clock from a slow typically 32 768 kHz or fast typically 4 194 MHz reference or uses an external frequency source Refer to Table 1 2 for i...

Page 28: ...ct line Each device has a comprehensive user s man ual that provides sufficient information for normal operation of the device The user s manual is supplemented by module reference manuals that provid...

Page 29: ...action two s complement or negation Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal AND Inclusive OR OR Exclusive OR EOR NOT Complementation Concatenation Transferr...

Page 30: ...unter extension field SK Stack pointer extension field SP Stack pointer XK Index register X extension field YK Index register Y extension field ZK Index register Z extension field XMSK Modulo addressi...

Page 31: ...Port QS Data Direction Register DREG SIM Test Module Distributed Register GPTMCR GPT Module Configuration Register GPTMTR GPT Module Test Register ICR GPT Interrupt Configuration Register ILSCI MCCI S...

Page 32: ...r QILR QSM Interrupt Level Register QIVR QSM Interrupt Vector Register QSMCR QSM Module Configuration Register QTEST QSM Test Register RAMBAH RAM Array Base Address Register High RAMBAL RAM Array Base...

Page 33: ...trol Register SYPCR SIM System Protection Control Register TCNT GPT Timer Counter Register TCTL 1 2 GPT Timer Control Registers 1 2 TFLG 1 2 GPT Timer Flag Registers 1 2 TI4 O5 GPT Timer Input Capture...

Page 34: ...s referred to by mnemonic and number A15 is bit 15 of accumulator A ADDR7 is line 7 of the address bus CSOR0 is chip select op tion register 0 A range of mnemonics is referred to by mnemonic and the n...

Page 35: ...ssor Unit CPU16 CPU16L 16 bit architecture Full set of 16 bit instructions Three 16 bit index registers Two 16 bit accumulators Control oriented digital signal processing capability Addresses up to 1...

Page 36: ...clock input 3 2 Intermodule Bus The intermodule bus IMB is a standardized bus developed to facilitate the design of modular microcontrollers It contains circuitry that supports exception processing ad...

Page 37: ...ace mount package Figure 3 6 shows an MC68HC16Z4 CKZ4 pin assignment drawing based on a 132 pin plastic surface mount package Figure 3 7 shows an MC68HC16Z4 CKZ4 pin assignment drawing based on a 144...

Page 38: ...E0 DSO CONTROL BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL PORT QS VDDA VSSA VRH VRL PWMA PWMB PCLK PAI CONTROL PORT GP OC2 OC1 PGP4 OC1 PGP3 IC4 OC5 OC1 PGP7 OC4 OC1 PGP6 OC3 OC1 PGP5 IC3 PGP2 IC2 PGP1...

Page 39: ...CONTROL BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL PORT QS VDDA VSSA VRH VRL PWMA PWMB PCLK PAI CONTROL PORT GP OC2 OC1 PGP4 OC1 PGP3 IC4 OC5 OC1 PGP7 OC4 OC1 PGP6 OC3 OC1 PGP5 IC3 PGP2 IC2 PGP1 IC1 PGP...

Page 40: ...E0 DSO CONTROL BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL PORT MCCI VDDA VSSA VRH VRL PWMA PWMB PCLK PAI CONTROL PORT GP OC2 OC1 PGP4 OC1 PGP3 IC4 OC5 OC1 PGP7 OC4 OC1 PGP6 OC3 OC1 PGP5 IC3 PGP2 IC2 PGP...

Page 41: ...0 ADDR19 CS6 PC3 119 BGACK CS2 118 BG CS1 117 TXD PQS7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 33 ADDR13 34...

Page 42: ...12 DSACK1 PE1 113 DSACK0 PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DATA6 128 DATA5 129 DATA4 130 NC 131 V...

Page 43: ...0 CS7 PC4 120 ADDR19 CS6 PC3 119 BGACK CS2 118 BG CS1 117 TXDA PMC7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12...

Page 44: ...PE4 111 AVEC PE2 112 DSACK1 PE1 113 DSACK0 PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DATA6 128 DATA5 129...

Page 45: ...onic Output Driver Input Synchronized Input Hysteresis Discrete I O Port Designation ADDR23 CS10 ECLK A Y N O ADDR 22 19 CS 9 6 A Y N O PC 6 3 ADDR 18 0 A Y N AN 7 0 1 Y N I PADA 7 0 AS B Y Y I O PE5...

Page 46: ...CK16Z4 4 PAI and PCLK can be used for discrete input but are not part of an I O port 5 PWMA and PWMB can be used for discrete output but are not part of an I O port Table 3 2 M68HC16 Z Series Driver...

Page 47: ...icrocontroller power Table 3 4 M68HC16 Z Series Signal Characteristics Signal Name MCU Module Signal Type Active State ADDR 23 0 SIM Bus AN 7 0 ADC Input AS SIM Output 0 AVEC SIM Input 0 BERR SIM Inpu...

Page 48: ...MCCI Input Output QUOT SIM Output R W SIM Output 1 0 RESET SIM Input Output 0 RXD QSM Input RXDA1 MCCI Input RXDB1 MCCI Input SCK QSM Input Output SCK1 MCCI Input Output SIZ 1 0 SIM Output 1 0 SS QSM...

Page 49: ...In Out Clock Serial I O and clock for background debug mode EXTAL XTAL Crystal Oscillator Connections for clock synthesizer circuit reference a crystal or an external oscillator can be used FC 2 0 Fu...

Page 50: ...R W Read Write Indicates the direction of data transfer on the bus RESET Reset System reset RXD Receive Data SCI Serial input to the SCI RXDA1 SCI A Receive Data Serial input from SCI A RXDB1 SCI B Re...

Page 51: ...AP ADC 64 BYTES GPT 64 BYTES SIM 128 BYTES SRAM CONTROL 8 BYTES QSM 512 BYTES YFFDFF YFFC00 YFFB07 YFFB00 YFFA7F YFFA00 YFF93F YFF900 YFF73F YFF700 1K SRAM ARRAY FFFFFF 000000 MAPPED TO 1K BOUNDARY Fr...

Page 52: ...L 32 BYTES YFF83F YFF820 FFFFFF 000000 2K SRAM ARRAY MAPPED TO 2K BOUNDARY Z2 ONLY 4K SRAM ARRAY MAPPED TO 4K BOUNDARY Z3 ONLY 8K ROM ARRAY MAPPED TO 8K BOUNDARY HC16Z4 CKZ4 ADDRESS MAP ADC 64 BYTES G...

Page 53: ...annot be relocated The CPU16 program counter stack pointer and Z index register can be initialized to any address in pseudolinear memory but exception vectors are limited to 16 bit address es To acces...

Page 54: ...13 14 15 16 17 18 19 37 38 FF VECTOR NUMBER TYPE OF EXCEPTION 0001FE 000000 INTERNAL REGISTERS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BA...

Page 55: ...19 37 38 FF VECTOR NUMBER TYPE OF EXCEPTION 0001FE 000000 INTERNAL REGISTERS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 020000 03000...

Page 56: ...16 17 18 19 37 38 FF VECTOR NUMBER TYPE OF EXCEPTION 0001FE 000000 INTERNAL REGISTERS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 02...

Page 57: ...4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 020000 030000 040000 050000 060000 070000 F80000 F90000 FA0000 FB0000 FC0000 FD0000 FE0000 FF0000 010000 080000 UN...

Page 58: ...ANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 020000 030000 040000 050000 060000 070000 F80000 F90000 FA0000 FB0000 FC0000 FD0000 FE0000 FF0000 010000 080000 UNDEFINED1 512 KBYTE...

Page 59: ...ANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 020000 030000 040000 050000 060000 070000 F80000 F90000 FA0000 FB0000 FC0000 FD0000 FE0000 FF0000 010000 080000 UNDEFINED1 51...

Page 60: ...OVERVIEW M68HC16 Z SERIES 3 26 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 61: ...egabyte address space There are no special instructions for I O that are separate from instructions for addressing memory Address space is made up of sixteen 64 Kbyte banks Specialized bank addressing...

Page 62: ...EGISTER Z SK SP STACK POINTER SP PK PC PROGRAM COUNTER PC CCR PK CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK EK XK YK ZK ADDRESS EXTENSION REGISTER K SK STACK EXTENSION FIELD SK MAC MULTIPLIER R...

Page 63: ...Z also provides an additional in dexed addressing capability that replaces M68HC11 direct addressing mode Initial IZ and ZK extension field values are included in the RESET exception vector so that ZK...

Page 64: ...B3 occurs during BCD addition EV Accumulator M Extension Overflow Flag EV is set when an overflow into AM31 has occurred N Negative Flag N is set under the following conditions When the MSB is set in...

Page 65: ...gned fractional multiplication and stores the cumulative result These operations are part of control oriented digital signal processing There are four MAC registers Register H contains the 16 bit sign...

Page 66: ...ntegers 16 bit signed fractions 32 bit signed fractions 36 bit signed fixed point numbers 20 bit effective addresses There are eight bits in a byte and 16 bits in a word Bit set and clear instructions...

Page 67: ...ess is normally an even byte address Byte 0 of a word has a lower 16 bit address than byte 1 Long words and 32 bit signed fractions consist of two consecutive words and are normally accessed at the ad...

Page 68: ...0 000A WORD 1 000C MSW LONG WORD 0 000E LSW LONG WORD 0 0010 MSW LONG WORD 1 0012 LSW LONG WORD 1 0014 Radix Point 16 BIT SIGNED FRACTION 0 0016 Radix Point 16 BIT SIGNED FRACTION 1 0018 Radix Point...

Page 69: ...ns use an 8 bit immediate mask operand to indi cate which registers must be pushed to or pulled from the stack Table 4 1 Addressing Modes Mode Mnemonic Description Accumulator Offset E X Index registe...

Page 70: ...dex register These modes are used for JMP and JSR instructions only 4 6 4 Inherent Addressing Mode Inherent mode instructions use information directly available to the processor to deter mine the effe...

Page 71: ...CPU16 instruction set is based on the M68HC11 instruction set but the opcode map has been rearranged to maximize performance with a 16 bit data bus Most M68HC11 code can run on the CPU16 following rea...

Page 72: ...6 ADCB Add with Carry to B B M C B IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT E X E Y E Z C3 D3 E3 F3 17C3 17D3 17E3 17F3 27C3 27D3 27E3 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6...

Page 73: ...to IY INH 375D 2 AEZ Add E to IZ INH 376D 2 AIS Add Immediate Data to Stack Pointer SK SP 20 IMM SK SP IMM8 IMM16 3F 373F ii jj kk 2 4 AIX Add Immediate Value to IX XK IX 20 IMM XK IX IMM8 IMM16 3C 3...

Page 74: ...D8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT 04 14 24 1704 1714 1724 1734 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 ASLA Arithmetic Shift Left A INH 3704 2 ASLB Arithmetic Shift Left B INH 3714 2 ASLD Ar...

Page 75: ...ggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 0 BCS2 Branch if Carry Set If C 1 branch REL8 B5 rr 6 2 BEQ2 Branch if Equal If Z 1 branch REL8 B7 rr 6 2 BGE2 Branch if Greater Than or Equal to Zero If N V...

Page 76: ...f rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10 12 10 12 10 12 10 14 10 14 10 14 10 14 BRN Branch Never If 1 0 branch REL8 B1 rr 2 BRSET2 Branch if Bit s Set If M Mask 0 branch I...

Page 77: ...E Y E Z 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 CMPB Compare B to Memory B M IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT E X E...

Page 78: ...X IND16 Y IND16 Z EXT 4D 5D 6D 377D 174D 175D 176D 177D ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 CPZ Compare IZ to Memory IZ M M 1 IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT 4E...

Page 79: ...ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 0 EORE Exclusive OR E E M M 1 E IMM16 IND16 X IND16 Y IND16 Z EXT 3734 3744 3754 3764 3774 jj kk gggg gggg gggg hh ll 4 6 6 6 6 0 FDIV Fractiona...

Page 80: ...3783 rrrr 6 4 LBLT2 Long Branch if Less Than Zero If N V 1 branch REL16 378D rrrr 6 4 LBMI2 Long Branch if Minus If N 1 branch REL16 378B rrrr 6 4 LBMV2 Long Branch if MV Set If MV 1 branch REL16 379...

Page 81: ...D8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT IMM16 CF DF EF 17CF 17DF 17EF 17FF 37BF ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 0 LDX Load IX M M 1 IX IND8 X IND8 Y IND8 Z IMM16 IND16 X IND...

Page 82: ...EXT to IXP EXT to EXT 30 32 37FE ff hh ll ff hh ll hh ll hh ll 8 8 10 0 MOVW Move Word M M 11 M M 12 IXP to EXT EXT to IXP EXT to EXT 31 33 37FF ff hh ll ff hh ll hh ll hh ll 8 8 10 0 MUL Multiply A...

Page 83: ...3767 3777 jj kk gggg gggg gggg hh ll 4 6 6 6 6 0 ORP 1 OR Condition Code Register CCR IMM16 CCR IMM16 373B jj kk 4 PSHA Push A SK SP 0001 SK SP Push A SK SP 0002 SK SP INH 3708 4 PSHB Push B SK SP 000...

Page 84: ...f ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 ROLA Rotate Left A INH 370C 2 ROLB Rotate Left B INH 371C 2 ROLD Rotate Left D INH 27FC 2 ROLE Rotate Left E INH 277C 2 ROLW Rotate Left Word IND16 X IND16 Y...

Page 85: ...17D2 17E2 17F2 27C2 27D2 27E2 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 SBCD Subtract with Carry from D D M M 1 C D IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT E X E Y E Z 82 9...

Page 86: ...4 4 6 6 6 6 0 STX Store IX IX M M 1 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT 8C 9C AC 178C 179C 17AC 17BC ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 0 STY Store IY IY M M 1 IND8 X IND8 Y IND8...

Page 87: ...nsfer B to A B A INH 3707 2 0 TBEK Transfer B to EK B 3 0 EK INH 27FA 2 TBSK Transfer B to SK B 3 0 SK INH 379F 2 TBXK Transfer B to XK B 3 0 XK INH 379C 2 TBYK Transfer B to YK B 3 0 YK INH 379D 2 TB...

Page 88: ...K IX INH 274F 2 TSY Transfer SP to Y SK SP 0002 YK IY INH 275F 2 TSZ Transfer SP to Z SK SP 0002 ZK IZ INH 276F 2 TXKB Transfer XK to B XK B 3 0 0 B 7 4 INH 37AC 2 TXS Transfer X to SP XK IX 0002 SK S...

Page 89: ...is not affected 2 Cycle times for conditional branches are shown in taken not taken order 3 CCR 15 0 change according to the copy of the CCR pulled from the stack 4 PK field changes according to the...

Page 90: ...egister X mask IND20 Y IY with signed 20 bit offset YMSK Modulo addressing index register Y mask IND20 Z IZ with signed 20 bit offset S Stop disable control bit INH Inherent MV AM overflow indicator I...

Page 91: ...uctions that either have been replaced by CPU16 instructions or that operate differently on the CPU16 Replacement instruc tions are not identical to M68HC11 CPU instructions M68HC11 code must be alter...

Page 92: ...Replaced by PSHM PSHY Replaced by PSHM PULX Replaced by PULM PULY Replaced by PULM RTI Reloads PC and CCR only RTS Uses two word stack frame SEC Replaced by ORP SEI Replaced by ORP SEV Replaced by OR...

Page 93: ...ndaries each instruction must contain an even number of bytes Operands are organized as bytes words or a combination of bytes and words Oper ands of four bits are either zero extended to eight bits or...

Page 94: ...tly All three may be active at any given time 8 Bit Opcode with 8 Bit Operand 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand 8 Bit Opcode with 4 Bit Index Extensions 15 14 13 12 11 10 9 8 7 6 5...

Page 95: ...FO that holds instructions while they are decoded and executed Depending upon instruction size as many as three instructions can be in the pipeline at one time single word instructions one held in sta...

Page 96: ...he change in flow When an instruction that causes a change in program flow executes PK PC point to the address of the first word of the instruction 0006 During execution of the instruc tion PK PC is l...

Page 97: ...ler in mind while reading this section 4 13 1 Exception Vectors An exception vector is the address of a routine that handles an exception Exception vectors are contained in a data structure called the...

Page 98: ...ial IZ Direct Page 4 0008 D Breakpoint 5 000A D Bus Error 6 000C D Software Interrupt 7 000E D Illegal Instruction 8 0010 D Division by Zero 9 E 0012 001C D Unassigned Reserved F 001E D Uninitialized...

Page 99: ...or IMB clocks but excep tion processing is synchronized For all asynchronous exceptions except RESET ex ception processing begins at the first instruction boundary following recognition of an excepti...

Page 100: ...tailed information con cerning interrupts and system reset For information concerning processing of specific exceptions refer to the CPU16 Reference Manual CPU16RM AD 4 13 6 RTI Instruction The return...

Page 101: ...s The signals provide a complete model of the pipeline up to the point a breakpoint is acknowledged Breakpoints are acknowledged after an instruction has executed when it is in pipeline stage C A brea...

Page 102: ...ended and special microcode performs debugging functions under external control While in BDM the CPU16 ceases to fetch instructions through the data bus and communicates with the development system th...

Page 103: ...ine from address PK PC 0006 FREEZE is negated before the first prefetch Upon negation of FREEZE the BDM serial subsystem is disabled and the DSO DSI signals revert to IPIPE0 IPIPE1 functionality Table...

Page 104: ...ode Data transfers occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is trans mitted MSB first and is latched on the rising edge of DSCLK The serial data wor...

Page 105: ...al task the algo rithms themselves typically consist of a series of multiply and accumulate MAC operations The CPU16 contains a dedicated set of registers that perform MAC oper ations As a group these...

Page 106: ...CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 46 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 107: ...les and external devices The system protection block provides bus and software watchdog monitors In addi tion it also provides a periodic interrupt timer to support execution of time critical con trol...

Page 108: ...range from 7FF000 to 7FFFFF when MM 1 register addresses range from FFF000 to FFFFFF In M68HC16 Z series MCUs ADDR 23 20 follow the logic state of ADDR19 unless externally driven MM corresponds to IM...

Page 109: ...determines what the external bus interface does during internal transfer op erations Table 5 1 shows whether data is driven externally and whether external bus arbitration can occur Refer to 5 6 6 1...

Page 110: ...ence is determined by the device A particular device cannot use both a fast and slow refer ence The fast reference is typically a 4 194 MHz crystal the slow reference is typically a 32 768 kHz crystal...

Page 111: ...n the EXTAL and XTAL pins Typically a 32 768 kHz crys tal is used for a slow reference but the frequency may vary between 25 kHz to 50 kHz Figure 5 3 shows a typical circuit Figure 5 3 Slow Reference...

Page 112: ...he other phase comparator input is a reference signal either from the crystal oscillator or from an external source The comparator generates a con trol signal proportional to the difference in phase b...

Page 113: ...the system clock frequency is one fourth the VCO frequency fVCO When X 1 a divide by two circuit is enabled and system clock frequency is one half the VCO frequency fVCO There is no relock delay when...

Page 114: ...cle of this signal is critical especially at operating frequencies close to maximum The relationship be tween clock signal duty cycle and clock signal period is expressed as follows Tables 5 2 5 3 and...

Page 115: ...100 52 40625 104 8125 208 1 625 416 3 25 001101 56 4375 112 875 224 1 75 448 3 5 001110 60 46875 120 9375 240 1 875 480 3 75 001111 64 5 128 1 256 2 512 4 010000 68 53125 136 1 0625 272 2 125 544 4 25...

Page 116: ...1 5625 400 3 125 800 6 25 1600 12 5 110010 204 1 59375 408 3 1875 816 6 375 1632 12 75 110011 208 1 625 416 3 25 832 6 5 1664 13 110100 212 1 65625 424 3 3125 848 6 625 1696 13 25 110101 216 1 6875 4...

Page 117: ...100 52 40625 104 8125 208 1 625 416 3 25 001101 56 4375 112 875 224 1 75 448 3 5 001110 60 46875 120 9375 240 1 875 480 3 75 001111 64 5 128 1 256 2 512 4 010000 68 53125 136 1 0625 272 2 125 544 4 25...

Page 118: ...1 5625 400 3 125 800 6 25 1600 12 5 110010 204 1 59375 408 3 1875 816 6 375 1632 12 75 110011 208 1 625 416 3 25 832 6 5 1664 13 110100 212 1 65625 424 3 3125 848 6 625 1696 13 25 110101 216 1 6875 4...

Page 119: ...100 52 40625 104 8125 208 1 625 416 3 25 001101 56 4375 112 875 224 1 75 448 3 5 001110 60 46875 120 9375 240 1 875 480 3 75 001111 64 5 128 1 256 2 512 4 010000 68 53125 136 1 0625 272 2 125 544 4 25...

Page 120: ...1 5625 400 3 125 800 6 25 1600 12 5 110010 204 1 59375 408 3 1875 816 6 375 1632 12 75 110011 208 1 625 416 3 25 832 6 5 1664 13 110100 212 1 65625 424 3 3125 848 6 625 1696 13 25 110101 216 1 6875 4...

Page 121: ...001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 17826 0100...

Page 122: ...10001 6554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 293...

Page 123: ...10486 001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 1782...

Page 124: ...554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 29360 5872...

Page 125: ...10486 001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 1782...

Page 126: ...554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 29360 5872...

Page 127: ...he following exceptions occur RESET Trace SIM interrupt of higher priority than the stored interrupt mask Refer to 5 6 4 2 LPSTOP Broadcast Cycle for more information During a low power stop mode unle...

Page 128: ...feclk fsys IN LPSTOP SET STEXT 0 fclkout 2 0 Hz feclk 0 Hz IN LPSTOP SET STEXT 1 fclkout 2 fref feclk 0 Hz IN LPSTOP SET STEXT 0 fclkout 2 0 Hz feclk 0 Hz IN LPSTOP ENTER LPSTOP NOTES 1 THE SIMCLK IS...

Page 129: ...P SET STEXT 0 fclkout 4 0 Hz feclk 0 Hz IN LPSTOP ENTER LPSTOP NOTES 1 IMBCLK IS THE CLOCK USED BY THE CPU16L SIML ADC MCCI AND THE GPT 2 WHEN STCPU 1 THE CPU16L IS SHUT DOWN IN LPSTOP ALL OTHER MODUL...

Page 130: ...C signal response times during normal bus cycles The monitor asserts the in ternal bus error BERR signal when the response time is excessively long DSACK and AVEC response times are measured in clock...

Page 131: ...sources of interrupt recognizes the highest priority source and then acquires a vector or responds to a request for autovectoring The spurious interrupt monitor asserts the internal bus error signal B...

Page 132: ...y where fref is equal to the EXTAL crystal frequency The following equation calculates the time out period for a fast reference frequency where fref is equal to the EXTAL crystal frequency The followi...

Page 133: ...ine interrupt timing priority and vector as signment Refer to 4 13 Exceptions for further information about interrupt exception processing Table 5 10 Software Watchdog Divide Ratio SWP SWT 1 0 Divide...

Page 134: ...he modulus counter value reaches zero an interrupt is generated The modulus counter is then reloaded with the value in PITM 7 0 and counting repeats If a new val ue is written to PITR it is loaded int...

Page 135: ...are watchdog timer is dis abled and the timer stops The software watchdog begins to run again on the first rising clock edge after low power stop mode ends The watchdog is not reset by low power stop...

Page 136: ...A 15 0 VDD E G A 14 0 DQ 7 0 W ADDR 15 1 DATA 15 8 VDD VDD E G A 14 0 DQ 7 0 W ADDR 15 1 DATA 7 0 VDD MC68HC681 MCM6206D M68HC16 Z SERIES MCU WE 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k ASYNC...

Page 137: ...ndicate the beginning of each bus cycle the address space the size of the transfer and the type of cycle External devices decode these signals and re spond to transfer data and terminate the bus cycle...

Page 138: ...always operates in supervisor mode FC2 1 address spaces 0 to 3 are not used Address space 7 is designated CPU space CPU space is used for control information not normally associated with read or writ...

Page 139: ...he same state If HALT is still asserted once bus mastership is returned to the MCU the ad dress function code size and read write signals are again driven to their previous states The MCU does not ser...

Page 140: ...CU transfers valid data The MCU always attempts to transfer the maximum amount of data on all bus cycles For a word operation it is assumed that the port is 16 bits wide when the bus cycle begins Oper...

Page 141: ...aps a word boundary This is determined by the value of ADDR0 When ADDR0 0 an even address the address is on a word and byte boundary When ADDR0 1 an odd address the address is on a byte boundary only...

Page 142: ...the interface signal timing constraints Although bus cycles are classified as asynchronous they are interpreted relative to the MCU system clock output CLKOUT Table 5 16 Operand Alignment Current Cyc...

Page 143: ...ead cycle To ensure valid data is latched into the MCU a maximum period between DSACK assertion and DS assertion is specified There is no specified maximum for the period between the assertion of AS a...

Page 144: ...Misaligned Operands for more infor mation Figure 5 13 is a flowchart of a write cycle operation for a word transfer Refer to the SIM Reference Manual SIMRM AD for more information RD CYC FLOW MCU PER...

Page 145: ...sociated DSACK fields must be programmed to the same value This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip se lects WR CYC FLOW M...

Page 146: ...use fast termination an external device must be fast enough to have data ready within the specified setup time for example by the falling edge of S4 Refer to AP PENDIX A ELECTRICAL CHARACTERISTICS fo...

Page 147: ...uring an operand fetch the acknowledge cycle occurs immediately after execution of the instruction during which it is latched If BKPT is asserted for only one bus cycle and a pipe flush occurs before...

Page 148: ...trol logic The mask is encoded on the data bus as shown in Figure 5 16 The LPSTOP CPU space cycle is shown externally if the bus is available as an indi cation to external devices that the MCU is goin...

Page 149: ...BERR to indicate an external bus error Halt signal HALT HALT can be asserted by an external device to cause single bus cycle opera tion HALT is typically used for debugging purposes To control termina...

Page 150: ...Because of these factors it is impossible to predict precisely how long after occur rence of a bus error the bus error exception is processed Table 5 17 DSACK BERR and HALT Assertion Results Type of...

Page 151: ...ted MCU However bus arbitration can still oc cur Refer to 5 6 6 External Bus Arbitration for more information A bus error or ad dress error that occurs after exception processing has been completed du...

Page 152: ...ol sequence is 1 An external device asserts the bus request signal BR 2 The MCU asserts the bus grant signal BG to indicate that the bus is available 3 An external device asserts the bus grant acknowl...

Page 153: ...us activity while there is an external master SIZ 1 0 signals reflect bus allocation during show cycles Only the appropriate portion of the data bus is valid during the cycle During a byte write to an...

Page 154: ...vector base register VBR The CPU16 uses vector numbers to calculate displacement into the table Refer to 4 13 Excep tions for more information Reset is the highest priority CPU16 exception Unlike all...

Page 155: ...BI Asynch VDD MSTRST CLKRST EXTRST Software watchdog Monitor Asynch Time out MSTRST CLKRST EXTRST HALT Monitor Asynch Internal HALT assertion e g double bus fault MSTRST CLKRST EXTRST Loss of clock Cl...

Page 156: ...before the first bus cycle after reset to prevent conflict with external memory devices The first bus cycle occurs ten CLKOUT cycles after RESET is re leased If external mode selection logic causes a...

Page 157: ...rent is specified in APPENDIX A ELECTRICAL CHARAC TERISTICS Do not confuse pin function with pin electrical state Refer to 5 7 5 Pin State During Reset for more information Unlike other chip select si...

Page 158: ...BKPT is sampled at a logic level one at the rising edge of RESET BDM is disabled Assertion of the BKPT pin or execution of the BKPT instruction will result in normal breakpoint exception processing BD...

Page 159: ...n ADC PADA 7 0 AN 7 0 Discrete input VRH Reference voltage VRL Reference voltage CPU DSI IPIPE1 DSI IPIPE1 DSO IPIPE0 DSO IPIPE0 BKPT DSCLK BKPT DSCLK GPT PGP7 IC4 OC5 Discrete input PGP 6 3 OC 4 1 Di...

Page 160: ...r On Reset for more information Table 5 21 SIM Pin Reset States Pin s Pin State While RESET Asserted Pin State After RESET Released Default Function Alternate Function Pin Function Pin State Pin Funct...

Page 161: ...end of this period the pin again goes to high impedance state for ten cycles then it is tested again The process repeats until external RESET is released 5 7 7 Power On Reset When the SIM clock synthe...

Page 162: ...igure 5 20 Power On Reset 5 7 8 Use of the Three State Control Pin Asserting the three state control TSC input causes the MCU to put all output drivers in a disabled high impedance state The signal mu...

Page 163: ...isabling MAC saturation mode C The K register is cleared NOTE All CCR bits that are not initialized are not affected by reset Howev er out of power on reset these bits are indeterminate The following...

Page 164: ...rupt requests are treated as interrupt service requests from the SIM Each of the interrupt request signals corresponds to an interrupt priority level IRQ1 has the lowest priority and IRQ7 the highest...

Page 165: ...mask field in the CPU16 condition code register to preclude further interrupts of lower priority during interrupt service Modules or external devices that have requested interrupt service must decode...

Page 166: ...ve their as sociated IACK cycles terminated with an internal DSACK Thus user vectors instead of autovectors must always be used for interrupts generated from internal modules If an internal module mak...

Page 167: ...CPU16 generates the spurious in terrupt vector number F The vector number is converted to a vector address G The content of the vector address is loaded into the PC and the processor transfers contro...

Page 168: ...A 15 0 VDD E G A 14 0 DQ 7 0 W ADDR 15 1 DATA 15 8 VDD VDD E G A 14 0 DQ 7 0 W ADDR 15 1 DATA 7 0 VDD MC68HC681 MCM6206D M68HC16 Z SERIES MCU WE 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k ASYNC...

Page 169: ...nals except CSBOOT are disabled and cannot be asserted until the BYTE 1 0 field in the corresponding option register is programmed to a non zero value to select a transfer size The chip select option...

Page 170: ...s provided to support bootstrap operation Comprehensive address maps and register diagrams are provided in APPENDIX D REGISTER SUMMARY 5 9 1 1 Chip Select Pin Assignment Registers The pin assignment r...

Page 171: ...pecified in the port C register No discrete output function is available on CSBOOT BR BG or BGACK ADDR23 provides the ECLK output rather than a discrete output signal When a pin is programmed for disc...

Page 172: ...determines whether chip select assertion simulates an asynchronous bus cycle or is synchronized to the M6800 type bus clock signal ECLK available on ADDR23 Refer to 5 3 System Clock for more informati...

Page 173: ...te output the value in this register appears at the output PC 6 0 correspond to CS 9 3 Bit 7 is not used Writing to this bit has no effect and it always reads zero 5 9 2 Chip Select Operation When the...

Page 174: ...sfers an interrupt ac knowledge cycle to the external address bus following IARB contention chip select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ p...

Page 175: ...in Table 5 25 The BYTE fields of CSOR 0 10 have a reset value of disable so that a chip select signal cannot be asserted until the base and option reg isters are initialized Following reset the MCU f...

Page 176: ...port F pin assignment registers PEPAR and PFPAR control the functions of the pins on each port Any bit set to one defines the corresponding pin as a bus control signal Any bit cleared to zero defines...

Page 177: ...alue read is the value stored in the register Both data registers can be accessed in two locations and can be read or written at any time 5 11 Factory Test The test submodule supports scan based testi...

Page 178: ...SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 72 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 179: ...are four SRAM control registers the RAM module configuration register RAM MCR the RAM test register RAMTST and the RAM array base address registers RAMBAH RAMBAL The module mapping bit MM in the SIM...

Page 180: ...nd program data space access Refer to 4 6 Addressing Modes for more in formation on addressing modes 6 4 Normal Access The array can be accessed by byte word or long word A byte or aligned word access...

Page 181: ...e a new base address into the ROMBAH and ROMBAL registers When a synchronous reset occurs while a byte or word SRAM access is in progress the access is completed If reset occurs during the first word...

Page 182: ...STANDBY RAM MODULE M68HC16 Z SERIES 6 4 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 183: ...ress for each M68HC16 M68CK16 and M68CM16 Z series module Because ADDR 23 20 are driven to the same value as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible For more informa...

Page 184: ...e CPU16 operates in supervisor mode only ASPC1 has no effect Table 7 1 shows ASPC 1 0 field encodings Refer to 5 5 1 7 Function Codes for more information concerning address space types and program da...

Page 185: ...f the MRM following reset is determined by the default values programmed into the MRMCR BOOT LOCK ASPC 1 0 and WAIT 1 0 bits The default array base address is determined by the values programmed into...

Page 186: ...MASKED ROM MODULE M68HC16 Z SERIES 7 4 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 187: ...ignals to the ADC Special operating modes and test functions are controlled by a module configuration register ADCMCR and a factory test register ADCTST ADC module conversion functions can be grouped...

Page 188: ...ferred to as PADA 7 0 There is no data direction register because port pins are input only 16 ADC BLOCK 2 RESULT 7 RESULT 6 RESULT 5 RESULT 4 RESULT 3 RESULT 2 RESULT 1 RESULT 0 SAR RC DAC ARRAY AND C...

Page 189: ...e configuration reg ister the test register and the port data register reside on the buffered bus while conversion registers and result registers reside on the differential bus Registers that reside o...

Page 190: ...in the analog conversion circuitry discharge while the ADC is frozen as a result the conversion will be inaccurate Refer to 4 14 4 Background Debug Mode for more information 8 6 Analog Subsystem The...

Page 191: ...period both sample capacitor and buffer ampli fier are bypassed and multiplexer input charges the DAC array directly The length of this third portion of a sampling period is determined by the value o...

Page 192: ...esolution sample time and clock prescal er value ADCTL1 controls analog input selection conversion mode and initiation of conversion A write to ADCTL0 aborts the current conversion sequence and halts...

Page 193: ...conversion results are automatically aligned in the result registers 8 7 5 Conversion Control Logic Analog to digital conversions are performed in sequences Sequences are initiated by any write to ADC...

Page 194: ...ion sequence is complete Table 8 5 Conversion Parameters Controlled by ADCTL1 Conversion Parameter Description Conversion channel The value of the channel selection field CD CA in ADCTL1 determines wh...

Page 195: ...annel specified by the value in CD CA Each result is stored in a separate result reg ister RSLT0 to RSLT7 Previous results are overwritten when a sequence repeats The appropriate CCF bit in ADCSTAT is...

Page 196: ...1 0 1 0 Reserved RSLT 0 3 0 1 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 VRH RSLT 0 3 0 1 1 0 1 VRL RSLT 0 3 0 1 1 1 0 VRH VRL 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 0 0 AN0 RSLT 0 7 1 0 0 0 1 AN1 R...

Page 197: ...RSLT0 AN5 RSLT1 AN6 RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLT0 Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X VRH RSLT0 VRL RSLT1 VRH VRL 2 RSLT2 Test Reserved RSLT3 1 0 X X X AN0 RSLT0 AN1 RSL...

Page 198: ...cles for 10 bit conversion Transfer and resolution require a minimum of 16 ADC clocks 8 s with a 2 1 MHz ADC clock for 8 bit resolution or 18 ADC clocks 9 s with a 2 1 MHz ADC clock for 10 bit resolut...

Page 199: ...s Result registers are used to store data after conversion is complete The registers can be accessed from the IMB under ABIU control Each register can be read from three different addresses in the ADC...

Page 200: ...must be within the lim its defined by VDDA and VSSA as explained in the following subsection 8 8 2 Analog Power Pins The analog supply pins VDDA and VSSA define the limits of the analog reference vol...

Page 201: ...VRL and VRH If VRH is greater than VDDA the sample amplifier can never transfer a full scale value If VRL is less than VSSA the sample am plifier can never transfer a zero value Figure 8 5 shows the...

Page 202: ...ly from a local digital supply is not recom mended However if for economic reasons digital and analog power are derived from a common regulator filtering of the analog power is recommended in addition...

Page 203: ...al voltage between the true analog ground and the microcontroller s ground pin The end result is that the ground observed by the analog circuit is no longer true ground and often ends in skewed result...

Page 204: ...t of the pin which exceed normal limits ADC specific con siderations are voltages greater than VDDA VRH or less than VSSA applied to an analog input which cause excessive currents into or out of the i...

Page 205: ...odes in a Negative Stress Circuit Another method for minimizing the impact of stress conditions on the ADC is to stra tegically allocate ADC inputs so that the lower accuracy inputs are adjacent to th...

Page 206: ...ETC R SOURCE2 C FILTER C SOURCE R FILTER2 CMUXIN 0 1 F1 R SOURCE2 C FILTER C SOURCE R FILTER2 CMUXIN 0 1 F1 R SOURCE2 C FILTER C SOURCE R FILTER2 CMUXIN 0 1 F1 R SOURCE2 C FILTER C SOURCE R FILTER2 C...

Page 207: ...istics required to accurately track the dynamic characteristics of an input Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog sign...

Page 208: ...The on resistance of the internal switches is zero ohms and the off resistance is infinite 8 8 6 1 Settling Time for the External Circuit The values for RF and CF in the user s external circuitry dete...

Page 209: ...age of 50 nA is present an error of 10 counts 50 mV is introduced In addition to internal junction leakage external leakage e g if external clamping di odes are used and charge sharing effects with in...

Page 210: ...ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 24 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 211: ...provides peripheral expansion or interprocessor communication through a full duplex synchronous three line bus Four programmable peripheral chip selects can select up to sixteen peripheral devices by...

Page 212: ...Global Registers The QSM configuration register QSMCR controls the interface between the QSM and the intermodule bus The QSM test register QTEST is used during factory test of the QSM The QSM interru...

Page 213: ...mpares the IP mask value to the priority of the interrupt request to determine whether it should contend for arbitration QSM arbitration priority is determined by the value of the IARB field in QSMCR...

Page 214: ...ers located at the same word address Refer to Table 9 1 for a summary of QSM pin functions Table 9 1 Effect of DDRQS on QSM Pin Function QSM Pin QSPI Mode DDRQS Bit Bit State Pin Function MISO Master...

Page 215: ...fer rates clocking and interrupt driven communication options is available Figure 9 2 displays a block diagram of the QSPI Figure 9 2 QSPI Block Diagram QSPI BLOCK CONTROL REGISTERS END QUEUE POINTER...

Page 216: ...uninterrupted bit stream of eight to 256 bits in length to be transferred without CPU16 intervention Longer transfers are possible but minimal intervention is required to prevent loss of data A standa...

Page 217: ...t to be read by the CPU16 Data stored in the receive RAM is right justified Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry The CPU16 can...

Page 218: ...and one word of receive data correspond to one queue entry 0 F The CPU16 initiates QSPI operation by setting up a queue of QSPI commands in com mand RAM writing transmit data into transmit RAM then e...

Page 219: ...lized properly In master mode the QSPI executes a queue of commands defined by control bits in each command RAM queue entry Chip select pins are activated data is transmitted from the transmit RAM and...

Page 220: ...IALIZE QSM GLOBAL REGISTERS INITIALIZE QSPI CONTROL REGISTERS INITIALIZE PQSPAR PORTQS AND DDRQS INITIALIZE QSPI RAM ENABLE QSPI BEGIN A2 QSPI INITIALIZATION MSTR 1 A1 Y N QSPI FLOW 1 IN THIS ORDER Fr...

Page 221: ...ED TO NEWQP IS QSPI DISABLED N Y N EXECUTE SERIAL TRANSFER STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS B1 QSPI CYCLE BEGINS MASTER MODE Y ASSERT PERIPHERAL CHIP SELECT S IS PCS TO SCK DELAY...

Page 222: ...AFTER TRANSFER ASSERTED Y N EXECUTE PROGRAMMED DELAY B1 WRITE QUEUE POINTER TO CPTQP STATUS BITS C1 NEGATE PERIPHERAL CHIP SELECT S Y N IS CONTINUE BIT ASSERTED EXECUTE STANDARD DELAY QSPI MSTR2 FLOW...

Page 223: ...ET WORKING QUEUE POINTER TO NEWQP OR 0000 Y DISABLE QSPI A1 N INCREMENT WORKING QUEUE POINTER N IS HALT OR FREEZE ASSERTED A1 HALT QSPI AND ASSERT HALTA N IS INTERRUPT ENABLE BIT HMIE ASSERTED REQUEST...

Page 224: ...NEWQP N Y N WRITE QUEUE POINTER TO CPTQP STATUS BITS STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS B2 QSPI CYCLE BEGINS SLAVE MODE Y EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED N Y IS SLAVE SE...

Page 225: ...ET WORKING QUEUE POINTER TO NEWQP OR 0000 Y DISABLE QSPI A2 N INCREMENT WORKING QUEUE POINTER N IS HALT OR FREEZE ASSERTED A2 HALT QSPI AND ASSERT HALTA N IS INTERRUPT ENABLE BIT HMIE ASSERTED REQUEST...

Page 226: ...he chip select pins MISO is used for serial data input in master mode and MOSI is used for serial data output Either or both may be nec essary depending on the particular application SCK is the serial...

Page 227: ...1 delay from chip select assertion until the leading edge of the serial clock The DSCKL field in SPCR1 determines the length of the user defined delay before the assertion of SCK The following expres...

Page 228: ...of 8192 fsys Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer Receiving devices need at least the stan...

Page 229: ...re it is complete If the SPIFIE bit in SPCR2 is set an interrupt request is generated when SPIF is asserted At this point the QSPI clears SPE and stops unless wrap around mode is enabled 9 3 5 2 Maste...

Page 230: ...e RAM Data is simultaneously loaded into the data serializer from the pointer address in transmit RAM and transmitted Transfer is synchronized with the externally generated SCK The CPHA and CPOL bits...

Page 231: ...an be connected to each PCS pin provided proper fanout is observed PCS0 shares a pin with the slave select SS signal which initiates slave mode serial transfer If SS is taken low when the QSPI is in m...

Page 232: ...Tx BUFFER SHIFT ENABLE JAM ENABLE PREAMBLE JAM 1 s BREAK JAM 0 s FORCE PIN DIRECTION OUT SIZE 8 9 PARITY GENERATOR TRANSMITTER BAUD RATE CLOCK TC TDRE SCI Rx REQUESTS SCI INTERRUPT REQUEST FE NF OR ID...

Page 233: ...OR IDLE RDRF TC TDRE SCSR STATUS REGISTER PF RAF 15 0 WAKE UP LOGIC PIN BUFFER RxD STOP 8 7 6 5 4 3 2 1 0 10 11 BIT Rx SHIFT REGISTER START MSB ALL ONES DATA RECOVERY 16 PARITY DETECT RECEIVER BAUD R...

Page 234: ...ction clears receiver sta tus flag bits that were set at the time of the read but does not clear TDRE or TC flags If an internal SCI signal for setting a status bit comes after reading the asserted st...

Page 235: ...by at least three receive time samples of logic one Stop Bit One bit time of logic one that indicates the end of a data frame Frame A complete unit of serial information The SCI can use 10 bit or 11...

Page 236: ...the bit period 9 4 3 4 Parity Checking The PT bit in SCCR1 selects either even PT 0 or odd PT 1 parity PT affects received and transmitted data The PE bit in SCCR1 determines whether parity check ing...

Page 237: ...to SCDR without first clearing TDRE the data will not be transmitted The transmission complete TC flag in SCSR shows transmitter shifter state When TC 0 the shifter is busy TC is set when all shifting...

Page 238: ...E bit in SCCR1 enables RE 1 and disables RE 0 the receiver The receiv er contains a receive serial shifter and a parallel receive data register RDR located in the SCI data register SCDR The serial shi...

Page 239: ...led The idle line type ILT bit in SCCR1 determines which type of detection is used When an idle line condition is detected the IDLE flag in SCSR is set For short idle line detection the receiver bit p...

Page 240: ...idle line between transmissions There must be no idle time between frames within a transmission Address mark wake up uses a special frame format to wake up the receiver When the MSB of an address mark...

Page 241: ...agram The SPI provides easy peripheral expansion or interprocessor communication via a full duplex synchronous three line bus data in data out and a serial clock Serial transfer of eight or sixteen bi...

Page 242: ...g for more in formation about how the state of MM affects the system 10 2 1 MCCI Global Registers The MCCI module configuration register MMCR contains bits and fields to place the MCCI in low power op...

Page 243: ...an the interrupt mask in the CPU status register the CPU initiates an interrupt acknowledge cycle During this cy cle the MCCI compares its interrupt request level to the level recognized by the CPU If...

Page 244: ...enable TE bits in the SCI control registers SCCR0A SCCR0B automatically assign the associ ated pin as an SCI pin when set or general purpose I O when cleared Table 10 2 summarizes how pin function and...

Page 245: ...s A slave select line allows individual selection of a slave SPI device Slave devices which are not selected do not interfere with SPI bus activities On a master SPI device the slave select line can o...

Page 246: ...master device initiates transmission or reception of another byte or word After a byte or word of data is transmitted the SPIF status bit is set in both the master and slave devices A read of the SPD...

Page 247: ...be used for general purpose I O 3 Write to the MDDR to direct the data flow on SPI pins Configure the SCK serial clock and MOSI pins as outputs Configure MISO and optionally SS as in puts 4 Write to...

Page 248: ...Write to the SPCR to assign values for CPHA CPOL SIZE LSBF WOMP and SPIE Set the MSTR bit to select master operation Set the SPE bit to enable the SPI The BAUD field in the SPCR of the slave device ha...

Page 249: ...icates the start of a transfer The SCK signal remains inactive for the first half of the first SCK cycle Data is latched on the first and each succeeding odd clock edge and the SPI shift register is l...

Page 250: ...he second and succeeding even clock edges SCK is inactive for the last half of the eighth SCK cycle For a master SPIF is set at the end of the eighth SCK cycle after the seventeenth SCK edge Since the...

Page 251: ...t open drain unless multiple SPI masters are in the system If needed the WOMP bit in SPCR can be set to provide wired OR open drain outputs An external pull up resistor should be used on each output l...

Page 252: ...periods and on avoiding write collision errors When a write collision occurs the WCOL bit in the SPSR is set To clear WCOL read the SPSR while WCOL is set and then either read the SPDR either before...

Page 253: ...h between the two SCI systems A reference to SCCR1 for example applies to both SCCR1A SCIA control register 1 and SCCR1B SCIB control register 1 10 4 1 SCI Registers The SCI programming model includes...

Page 254: ...JAM 1 S PIN BUFFER AND CONTROL L 0 1 2 3 4 5 6 7 8 H STOP 10 11 BIT TX SHIFT REGISTER START MDDR7 MDDR5 FORCE PIN DIRECTION OUT SCDR TX BUFFER INTERNAL DATA BUS GENERATOR 15 0 WOMS PT PE M WAKE TIE T...

Page 255: ...FT REGISTER START INTERNAL DATA BUS 15 0 WOMS PT PE M WAKE TIE TCIE RIE ILIE TE RE RWU SBK SCSR STATUS REGISTER 15 0 TDRE TC RDRF RAF IDLE OR NF FE PF SCI TX REQUESTS SCI INTERRUPT REQUEST BAUD RATE C...

Page 256: ...et and the SCDR must be written to or read before the status bit is cleared Reading either byte of the SCSR causes all 16 bits to be accessed and any status bit already set in either byte will be clea...

Page 257: ...ber of formats The following terms con cerning data format are used in this section Bit Time The time required to transmit or receive one bit of data which is equal to one cycle of the baud frequency...

Page 258: ...zero SCCR0 The baud rate is derived from the MCU system clock by a modulus counter Writing a value of zero to SCBR 12 0 disables the baud rate generator Baud rate is calculated as follows or where SCB...

Page 259: ...should be specified when more than one transmitter is used on the same SCI bus The WOMS bit in SCCR1 determines whether TXD is an open drain wired OR output or a normal CMOS output An external pull up...

Page 260: ...re a mark on the TXD pin even when the transmitter is disabled Configure the TXD pin as an output then write a one to PQS7 When the transmitter releases control of the TXD pin it reverts to driving a...

Page 261: ...and PF cannot occur at the same time as OR When the CPU16 reads SCSR and SCDR in sequence it acquires status and data and also clears the status flags Reading SCSR acquires status and arms the cleari...

Page 262: ...ng and recognition scheme Idle line wake up allows a receiver to sleep until an idle line is detected When an idle line is detected the receiver clears RWU and wakes up The receiver waits for the firs...

Page 263: ...Write a transfer rate value into the BAUD field b Determine clock phase CPHA and clock polarity CPOL c Specify an 8 or 16 bit transfer SIZE and MSB or LSB first transfer mode LSBF d Select master or...

Page 264: ...MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 24 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 265: ...pare These channels share a 16 bit free running counter TCNT that derives its clock from a nine stage prescaler or from the external clock input signal PCLK Pulse accumulator channel logic includes an...

Page 266: ...perations Certain capture compare registers and pulse width modulation registers must be accessed by word operations to ensure coherency If byte accesses are used to read a register such as the timer...

Page 267: ...are used to determine what action is taken by the GPT when the IMB FREEZE signal is asserted FREEZE is asserted when the CPU enters background debug mode At the present time FRZ1 is not implemented F...

Page 268: ...d interrupt The timer interrupt flag registers TFLG1 and TFLG2 contain status flags used for polled and interrupt driven opera tion The timer mask registers TMSK1 and TMSK2 contain interrupt control b...

Page 269: ...is a corresponding bit in TFLG1 and TFLG2 in the same bit position TMSK2 also controls the operation of the timer prescaler Refer to 11 7 Prescaler for more information The value of the interrupt prio...

Page 270: ...n ment is shown in Table 11 2 At reset IVBA 3 0 is initialized to 0 To enable interrupt driven timer operation the upper nibble of a user defined vector number 40 FF must be written to IVBA and interr...

Page 271: ...by either an input cap ture or an output compare function It has an associated 16 bit register that is used for holding either the input capture value or the output match value When used for input cap...

Page 272: ...is read from and written to the port GP data register PORTGP Pin data can be read even when pins are configured for a timer function Data read from PORT GP always reflects the state of the external p...

Page 273: ...WM counter PWMCNT is selected by bits PPR 2 0 in PWM control register C PWMC After re set the GPT is configured to use system clock divided by four for TCNT and system clock divided by two for PWMCNT...

Page 274: ...stopped during normal operation After reset the GPT is configured to use the system clock divided by four as the input to the counter The prescaler divides the system clock and provides selectable inp...

Page 275: ...TOC4 LO 16 BIT COMPARATOR TI4 O5 HI TI4 O5 LO 16 BIT FREE RUNNING COUNTER TCNT HI TCNT LO 9 TOI TOF INTERRUPT REQUESTS PRESCALER DIVIDE BY 4 8 16 32 64 128 256 CPR2 CPR1 16 BIT TIMER BUS OC5 IC4 1 2...

Page 276: ...on Input capture events are generally asynchronous to the timer counter Because of this input capture signals are conditioned by a synchronizer and digital filter Events are synchronized with the syst...

Page 277: ...hen the programmed content of an output compare register matches the value in TCNT an output compare status flag OCxF bit in TFLG1 is set If the appropriate in terrupt enable bit OCxI in TMSK1 is set...

Page 278: ...nnels take programmed actions immediately after the write to CFORC The CFORC register is implemented as the upper byte of a 16 bit register which also contains the PWM control register C PWMC It can b...

Page 279: ...pulse accumulator flag PAIF indicates that a selected edge has been detected at the PAI pin The pulse accumulator overflow flag PAOVF indicates that the pulse accumulator count has rolled over from F...

Page 280: ...dge is detected In gated mode PEDGE specifies the active state of the gate signal Bits PACLK 1 0 select the clock source used in gated mode PACTL and PACNT are implemented as one 16 bit register but c...

Page 281: ...trolled by software The PWMA pin can also output the clock that drives the PWM counter PWM pins can also be used as output pins 16 32 PWM BLOCK ZERO DETECTOR 16 BIT COUNTER PWMA REGISTER PWMB REGISTER...

Page 282: ...cessed as separate bytes or as one 16 bit register A value of 00 loaded into either register causes the corresponding output pin to output a continuous logic level zero signal A value of 80 causes the...

Page 283: ...reset These registers may be written or read at any time PWMC is implemented as the lower byte of a 16 bit register The upper byte is the CFORC register The buffer registers PWMBUFA and PWMBUFB are re...

Page 284: ...GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 20 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 285: ...quired current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values VIN 0 3 to 6 5 V 3 Instantaneous Maximum Current Single Pin...

Page 286: ...pply Current 4 194 MHz VCO on maximum fsys 32 768 kHz VCO on maximum fsys 4 194 MHz External Clock maximum fsys 32 768 kHz External Clock maximum fsys 4 194 MHz LPSTOP VCO off 32 768 kHz LPSTOP VCO of...

Page 287: ...eration Standby operation ISB 1 0 1 0 A A 8 Power Dissipation PD 380 mW Table A 4 Typical Ratings 20 97 MHz Operation Num Rating Symbol Value Unit 1 Supply Voltage VDD 5 0 V 2 Operating Temperature TA...

Page 288: ...0 125 3 75 mA A mA 4 Clock Synthesizer Operating Voltage VDDSYN 5 0 V 5 VDDSYN Supply Current VCO on maximum fsys External Clock maximum fsys LPSTOP VCO off VDD powered down IDDSYN 1 0 5 0 100 50 mA m...

Page 289: ...Dissipation on Input and Output Pins User Determined For most applications PI O PINT and can be neglected An approximate relationship between PD and TJ if PI O is neglected is 2 Solving equations 1 an...

Page 290: ...n Chip PLL System Frequency Fast On Chip PLL System Frequency External Clock Operation fsys dc 4 fref 4 fref 128 dc 16 78 16 78 16 78 16 78 MHz 4 PLL Lock Time1 7 8 9 Changing W or Y in SYNCR or exiti...

Page 291: ...Frequency Fast On Chip PLL System Frequency External Clock Operation fsys dc 4 fref 4 fref 128 dc 16 78 16 78 16 78 16 78 MHz 3 PLL Lock Time1 7 8 9 Changing W or Y in SYNCR or exiting from LPSTOP3 W...

Page 292: ...Frequency Fast On Chip PLL System Frequency External Clock Operation fsys dc 4 fref 4 fref 128 dc 20 97 20 97 20 97 20 97 MHz 3 PLL Lock Time1 7 8 9 Changing W or Y in SYNCR or exiting from LPSTOP3 W...

Page 293: ...frequency fVCO is determined by SYNCR W and Y bit values The SYNCR X bit controls a di vide by two circuit that is not in the synthesizer feedback loop When X 0 the divider is enabled and fsys fVCO 4...

Page 294: ...Voltage VIHTSC 7 2 9 1 V 11 Data Bus Mode Select Pull up Current 4 Vin VIL Vin VIH IMSP 8 95 A 12 VDD Supply Current5 Run6 LPSTOP 4 194 MHz crystal VCO Off STSIM 0 7 LPSTOP 32 768 kHz crystal VCO Off...

Page 295: ...R mode 4 Use of an active pulldown device is recommended 5 Total operating current is the sum of the appropriate IDD IDDSYN ISB and IDDA 6 Current measured with system clock frequency of 16 78 MHz all...

Page 296: ...t9 10 Vin VIL Vin VIH IMSP 15 120 A 12 MC68HC16Z1 VDD Supply Current11 12 13 Run LPSTOP crystal VCO Off STSIM 0 LPSTOP external clock input frequency maximum fsys IDD 110 350 5 mA A mA 12A MC68HC16Z2...

Page 297: ...6Z1 Power Dissipation16 PD 639 mW 17A MC68HC16Z2 Z3 Power Dissipation16 PD 666 mW 18 Input Capacitance3 7 13 All input only pins except ADC pins All input output pins CIN 10 20 pF 19 Load Capacitance4...

Page 298: ...in VIL Vin VIH IMSP 15 120 A 12 MC68HC16Z1 VDD Supply Current11 12 13 Run LPSTOP crystal VCO Off STSIM 0 LPSTOP external clock input frequency maximum fsys IDD 140 350 5 mA A mA 12A MC68HC16Z2 Z3 VDD...

Page 299: ...C16Z1 Power Dissipation16 PD 772 mW 17A MC68HC16Z2 Z3 Power Dissipation16 PD 787 mW 18 Input Capacitance3 7 13 All input only pins except ADC pins All input output pins CIN 10 20 pF 19 Load Capacitanc...

Page 300: ...n VIL Vin VIH IMSP 15 120 A 12 MC68HC16Z1 VDD Supply Current11 12 13 Run LPSTOP crystal VCO Off STSIM 0 LPSTOP external clock input frequency maximum fsys IDD 140 350 5 mA A mA 12A MC68HC16Z2 Z3 VDD S...

Page 301: ...ns except ADC pins 4 Input Only Pins EXTAL TSC BKPT DSCLK PAI PCLK RXD Input Output CSBOOT BG CS1 CLKOUT FREEZE QUOT DSO IPIPE0 PWMA PWMB Output Only Pins Group 1 Port GP 7 0 IC4 OC5 OC1 IC 3 1 OC 4 1...

Page 302: ...dby mode 15 When VSB is more than 0 3 V greater than VDD current flows between the VSTBY and VDD pins which causes standby current to increase toward the maximum transient condition specification Syst...

Page 303: ...13 AS DS CS Negated to ADDR FC SIZ Invalid Address Hold tSNAI 15 ns 14 AS CS and DS Read Width Asserted tSWA 110 ns 14A DS CS Width Asserted Write tSWAW 45 ns 14B AS CS and DS Read Width Asserted Fas...

Page 304: ...RADC 40 ns 70 Clock Low to Data Bus Driven Show Cycle tSCLDD 0 30 ns 71 Data Setup Time to Clock Low Show Cycle tSCLDS 15 ns 72 Data Hold from Clock Low Show Cycle tSCLDH 10 ns 73 BKPT Input Setup Tim...

Page 305: ...S DS CS Negated to ADDR FC SIZE Invalid Address Hold tSNAI 15 ns 14 AS CS and DS Read Width Asserted tSWA 100 ns 14A DS CS Width Asserted Write tSWAW 45 ns 14B AS CS and DS Read Width Asserted Fast Cy...

Page 306: ...ange tRADC 40 ns 70 Clock Low to Data Bus Driven Show Cycle tSCLDD 0 29 ns 71 Data Setup Time to Clock Low Show Cycle tSCLDS 15 ns 72 Data Hold from Clock Low Show Cycle tSCLDH 10 ns 73 BKPT Input Set...

Page 307: ...AS DS CS Negated to ADDR FC SIZE Invalid Address Hold tSNAI 10 ns 14 AS CS and DS Read Width Asserted tSWA 80 ns 14A DS CS Width Asserted Write tSWAW 36 ns 14B AS CS and DS Read Width Asserted Fast Cy...

Page 308: ...hange tRADC 32 ns 70 Clock Low to Data Bus Driven Show Cycle tSCLDD 0 23 ns 71 Data Setup Time to Clock Low Show Cycle tSCLDS 10 ns 72 Data Hold from Clock Low Show Cycle tSCLDH 10 ns 73 BKPT Input Se...

Page 309: ...AS DS CS Negated to ADDR FC SIZ Invalid Address Hold tSNAI 8 ns 14 AS CS and DS Read Width Asserted tSWA 65 ns 14A DS CS Width Asserted Write tSWAW 25 ns 14B AS CS and DS Read Width Asserted Fast Cycl...

Page 310: ...ut Setup Time tBKST 10 ns 74 BKPT Input Hold Time tBKHT 10 ns 75 Mode Select Setup Time DATA 15 0 MODCLK BKPT tMSS 20 tcyc 76 Mode Select Hold Time DATA 15 0 MODCLK BKPT tMSH 0 ns 77 RESET Assertion T...

Page 311: ...ts being used for synchronous ECLK cycles 7 Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads The user is free to use either hold t...

Page 312: ...g Diagram 16 CLKOUT TIM 4 CLKOUT 5 2 3 1 16 EXT CLK INPUT TIM 4B EXTAL 5B 2B 3B 1B NOTE TIMING SHOWN WITH RESPECT TO VIH VIL LEVELS PULSE WIDTH SHOWN WITH RESPECT TO 50 VDD 16 ECLK OUTPUT TIM 4A ECLK...

Page 313: ...105 47B 47A 102 100 101 104 48 27A 27 29A 28 20 31 29 47A 46 18 21 9A 9 11 12 13 15 8 6 ADDR 23 0 FC 2 0 SIZ 1 0 DS CS R W AS DSACK0 DSACK1 DATA 15 0 BERR HALT BKPT ASYNCHRONOUS INPUTS IPIPE0 IPIPE1...

Page 314: ...4 S5 48 27A 28 17 25 20 9 11 14 12 13 15 8 6 ADDR 23 20 FC 2 0 SIZ 1 0 DS CS R W AS DSACK0 DSACK1 DATA 15 0 BERR HALT BKPT 54 53 55 47A 46 26 23 9 74 73 103 105 102 100 101 104 IPIPE0 IPIPE1 PHASE 1 P...

Page 315: ...am CLKOUT S0 S1 S4 S5 S0 18 9 6 ADDR 23 0 FC 2 0 SIZ 1 0 DS CS R W AS DATA 15 0 8 BKPT 12 46A 30 29A 20 74 30A 29 PHASE 1 PHASE 2 100 102 104 103 105 101 IPIPE0 IPIPE1 27 73 14B 16 FAST RD CYC TIM Fre...

Page 316: ...Diagram CLKOUT S0 S1 S4 S5 S0 20 9 6 ADDR 23 0 FC 1 0 SIZ 1 0 DS CS R W AS DATA 15 0 14B 8 BKPT 100 101 IPIPE0 IPIPE1 PHASE 1 12 46A 23 73 PHASE 2 24 18 25 16 FAST WR CYC TIM 105 102 104 103 Freescal...

Page 317: ...us Case 16 BUS ARB TIM CLKOUT S0 S1 S2 S3 S4 ADDR 23 0 DATA 15 0 7 S98 A5 A5 A2 47A 39A 35 33 33 16 S5 AS DS R W DSACK0 DSACK1 BR BG BGACK 37 PHASE 1 PHASE 2 100 102 104 103 105 101 IPIPE0 IPIPE1 Free...

Page 318: ...A 9 Bus Arbitration Timing Diagram Idle Bus Case 16 BUS ARB TIM IDLE CLKOUT A0 A5 ADDR 23 0 DATA 15 0 A2 A3 A0 A5 BR AS BG BGACK 47A 33 33 47A 37 47A 35 Freescale Semiconductor I Freescale Semiconduct...

Page 319: ...20 SHOW CYCLE START OF EXTERNAL CYCLE 74 S43 16 SHW CYC TIM PHASE 1 PHASE 2 PHASE 1 PHASE 2 100 102 104 103 105 101 73 IPIPE0 IPIPE1 NOTE SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESS...

Page 320: ...TIM 6 6 8 11 11 25 53 54 23 55 29A 29 27 46 46 14A 13 15 9 9 12 14 9 18 20 18 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 14 CLKOUT ADDR 23 0 FC 2 0 SIZ 1 0 AS DS CS R W DATA 15 0 21 17 17 12 16 RST MODE SEL...

Page 321: ...Asserted tIPFA TBD tcyc B11 FREEZE Negated to IPIPE 0 1 Active tFRIP TBD tcyc Table A 20 16 78 MHz Background Debug Mode Timing VDD and VDDSYN 5 0 Vdc 10 VSS 0 Vdc TA TL to TH 1 NOTES 1 All AC timing...

Page 322: ...rted tIPFA TBD tcyc B11 FREEZE Negated to IPIPE 0 1 Active tFRIP TBD tcyc Table A 22 25 17 MHz Background Debug Mode Timing VDD and VDDSYN 5 0 Vdc 5 VSS 0 Vdc TA TL to TH 1 NOTES 1 All AC timing is sh...

Page 323: ...Figure A 14 Background Debug Mode Timing Diagram Freeze Assertion 16 BDM SER COM TIM B1 B3 B2 B0 B4 CLKOUT FREEZE BKPT DSCLK IPIPE1 DSI IPIPE0 DSO B5 B9 16 BDM FRZ TIM B8 CLKOUT FREEZE IPIPE1 DSI B6...

Page 324: ...dth tECSN 30 ns E6 Read Data Setup Time tEDSR 30 ns E7 Read Data Hold Time tEDHR 15 ns E8 ECLK Low to Data High Impedance tEDHZ 60 ns E9 CS Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data...

Page 325: ...tECSN 30 ns E6 Read Data Setup Time tEDSR 30 ns E7 Read Data Hold Time tEDHR 15 ns E8 ECLK Low to Data High Impedance tEDHZ 60 ns E9 CS Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data Hig...

Page 326: ...tECSN 25 ns E6 Read Data Setup Time tEDSR 25 ns E7 Read Data Hold Time tEDHR 5 ns E8 ECLK Low to Data High Impedance tEDHZ 48 ns E9 CS Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data High...

Page 327: ...CSH 10 ns E5 CS Negated Width tECSN 20 ns E6 Read Data Setup Time tEDSR 25 ns E7 Read Data Hold Time tEDHR 5 ns E8 ECLK Low to Data High Impedance tEDHZ 40 ns E9 CS Negated to Data Hold Read tECDH 0 n...

Page 328: ...Timing Diagram HC16 E CYCLE TIM CLKOUT ADDR 23 0 CS ECLK DATA 15 0 E1 2A 3A E2 E5 E4 E3 E9 E7 E8 E10 E12 E15 E14 1A DATA 15 0 E16 E11 WRITE READ WRITE E6 R W E13 Freescale Semiconductor I Freescale Se...

Page 329: ...High or Low Time Master Slave2 tsw 2 tcyc 60 2 tcyc n 255 tcyc ns ns 6 Sequential Transfer Delay Master Slave Does Not Require Deselect ttd 17 13 8192 tcyc tcyc 7 Data Setup Time Inputs Master Slave...

Page 330: ...Low Time Master Slave2 2 For high time n External SCK rise time for low time n External SCK fall time tsw 2 tcyc 60 2 tcyc n 255 tcyc ns ns 6 Sequential Transfer Delay Master Slave Does Not Require D...

Page 331: ...T DATA LSB OUT PORT DATA 7 12 13 PCS 3 0 OUTPUT PD MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 16 QSPI MAST CPHA1 13 11 10 12 4 4 13 12 3 2 5 1 MSB PCS 3 0 OUTPUT MISO INPUT MSB MSB OUT...

Page 332: ...MSB OUT MSB IN DATA LSB IN SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT MISO OUTPUT MOSI INPUT 4 16 QSPI SLV CPHA0 16 QSPI SLV CPHA1 SS INPUT 13 12 4 12 5 11 12 6 10 9 8 DATA SLAVE LSB OUT PD MSB OUT MS...

Page 333: ...High or Low Time Master Slave2 tsw 2 tcyc 60 2 tcyc n 255 tcyc ns ns 6 Sequential Transfer Delay Master Slave Does Not Require Deselect ttd 17 13 8192 tcyc tcyc 7 Data Setup Time Inputs Master Slave t...

Page 334: ...Low Time Master Slave2 2 For high time n External SCK rise time for low time n External SCK fall time tsw 2 tcyc 60 2 tcyc n 255 tcyc ns ns 6 Sequential Transfer Delay Master Slave Does Not Require De...

Page 335: ...MSB IN MSB OUT DATA LSB OUT PORT DATA 7 12 13 PD MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 16 MCCI MAST CPHA1 13 11 10 12 4 4 13 12 1 MSB MISO INPUT MSB MSB OUT DATA LSB OUT PORT DAT...

Page 336: ...OUT MSB IN DATA LSB IN SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT MISO OUTPUT MOSI INPUT 4 16 MCCI SLV CPHA0 12 16 MCCI SLV CPHA1 SS INPUT 13 12 4 12 5 11 12 6 10 9 8 DATA SLAVE LSB OUT PD MSB OUT MS...

Page 337: ...ut Capture PWtim 2 Fclock 4 PWM Resolution 2 Fclock 5 IC OC Resolution 4 Fclock 6 PCLK Width PWM 4 Fclock 7 PCLK Width IC OC 4 Fclock 8 PAI Pulse Width 2 Fclock NOTES 2 A INPUT SIGNAL AFTER THE SYNCHR...

Page 338: ...QUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 4 THE EXTERNAL LEADING EDGE CAUSES THE PULSE ACCUMULATOR TO INCREMENT AND THE PAIF FLAG TO BE SET 5 THE COUNTER TRANSITION FROM FF T...

Page 339: ...THE DIGITAL FILTER 2 PHI1 4 CLOCKS PACNT WHEN GT PAIF IS ASSERTED 5 PAIF IS ASSERTED WHEN PAI IS NEGATED 1 PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING PAI...

Page 340: ...ES NOT HAVE THE SAME TIMING PACNT PULSE ACCUM TOF GATED MODE PAI SIGNAL IS ASSERTED TCNT EXT PIN PAI PHI1 42 PHI11 FF 00 01 02 NOTES 2 WHEN THE COUNTER ROLLS OVER FROM FF TO 00 THE PWM PIN IS SET TO L...

Page 341: ...REGISTER THE OCx FLAG IS SET FOLLOWED BY THE OCx PIN 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING EXT PIN OCx OUTPUT COMPARE OCxF OCx MATCH TCNT2 OCx COMPA...

Page 342: ...T TO BE LATCHED BY THE ICx 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING ICxF INPUT CAPTURE CAPTURE REGISTER THE ICxF FLAG IS SET AT THE SAME TIME ICx CAPTU...

Page 343: ...IT AS 1 IMB READ CYCLE READ BIT AS 0 NOTES 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING INTERNAL GENERAL PURPOSE INPUT DATA BUS PDRx CONDITIONED INPUT EXTE...

Page 344: ...PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING PHI11 GENERAL PURPOSE OUTPUT IT CAUSES THE CONTENTS OF THE TCNT TO BE LATCHED INTO THE ICx COMPARE REGISTER BUS...

Page 345: ...ES COMPARE COMPARE CLOCK TCNT TOCx FOCx OCxF NOT SET EXTERNAL PIN OCx NOTES 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING FORCE COMPARE B1 B2 B3 B4 B1 B2 B3...

Page 346: ...essed channels Transitions within the limit do not affect device reliability or cause permanent damage 4 Input must be current limited to the value specified To determine the value of the required cur...

Page 347: ...2 VDDA V 11 Analog Supply Current Normal Operation4 Low Power Stop 4 Current measured at maximum system clock frequency with ADC active IDDA 1 0 200 mA A 12 Reference Supply Current IREF 120 A 13 Inpu...

Page 348: ...2 V 6 Reference Voltage High2 3 VRH VDDA 2 VDDA V 7 VREF Differential Voltage3 VRH VRL 4 5 5 5 V 8 Input Voltage2 VINDC VSSA VDDA V 9 Input High Port ADA VIH 0 7 VDDA VDDA 0 3 V 10 Input Low Port ADA...

Page 349: ...nit 1 ADC Clock Frequency fADCLK 0 5 2 1 MHz 2 8 Bit Conversion Time1 fADCLK 1 0 MHz fADCLK 2 1 MHz NOTES 1 Conversion accuracy varies with fADCLK rate Reduced conversion accuracy occurs at maximum tC...

Page 350: ...10 Bit Absolute Error3 4 4 10 bit absolute error of 4 0 counts 12 mV includes 1 2 count 1 5 mV inherent quantization error and 3 5 counts 10 5 mV circuit differential integral and offset error AE 4 4...

Page 351: ...2 0 2 0 Counts 8 10 Bit Absolute Error3 4 4 10 bit absolute error of 2 5 counts 12 5 mV includes 1 2 count 2 5 mV inherent quantization error and 2 counts 10 mV circuit differential integral and offs...

Page 352: ...T E E R R O R B O U N D A R Y B 8 BIT TRANSFER CURVE NO CIRCUIT ERROR DIGITAL OUTPUT A B C CIRCUIT CONTRIBUTED 12 mV ERROR 18 mV ABSOLUTE ERROR 1 5 8 BIT COUNTS IDEAL TRANSFER CURVE 1 2 COUNT 6 mV IN...

Page 353: ...R R O R B O U N D A R Y 2 0 m V 8 B I T A B S O L U T E E R R O R B O U N D A R Y B C 8 BIT TRANSFER CURVE NO CIRCUIT ERROR DIGITAL OUTPUT A A B C 1 2 COUNT 10 mV INHERENT QUANTIZATION ERROR CIRCUIT C...

Page 354: ...O L U T E E R R O R B O U N D A R Y 10 BIT TRANSFER CURVE NO CIRCUIT ERROR IDEAL TRANSFER CURVE DIGITAL OUTPUT A B C 5 COUNT 1 5 mV INHERENT QUANTIZATION ERROR CIRCUIT CONTRIBUTED 10 5 mV ERROR 12 mV...

Page 355: ...E E R R O R B O U N D A R Y 10 BIT TRANSFER CURVE NO CIRCUIT ERROR IDEAL TRANSFER CURVE DIGITAL OUTPUT A B C 5 COUNT 2 5 mV INHERENT QUANTIZATION ERROR CIRCUIT CONTRIBUTED 10 mV ERROR 12 5 mV ABSOLUTE...

Page 356: ...ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 72 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 357: ...G INFORMATION M68HC16 Z series microcontrollers are available in both 132 and 144 pin packages This appendix provides package pin assignment drawings dimensional drawings and ordering information Free...

Page 358: ...DDR20 CS7 PC4 120 ADDR19 CS6 PC3 119 BGACK CS2 118 BG CS1 117 TXD PQS7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 ADDR11 32 ADDR...

Page 359: ...S8 PC5 121 ADDR20 CS7 PC4 120 ADDR19 CS6 PC3 119 BGACK CS2 118 BG CS1 117 TXDA PMC7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 A...

Page 360: ...AUSE THE LEAD WIDTH TO EXCEED 0 019 L L M 0 016 N H A1 S J A S1 J1 1 17 117 18 116 50 84 51 83 VIEW AB PIN 1 IDENT AA AA V1 B1 P V B P1 2X 0 002 L M 4X 2X 0 002 N 4X 0 004 T C1 4X 33 TIPS C2 C SEATING...

Page 361: ...4 111 AVEC PE2 112 DSACK1 PE1 113 DSACK0 PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DATA6 128 DATA5 129 DA...

Page 362: ...09 AS PE5 110 DS PE4 111 AVEC PE2 112 DSACK1 PE1 113 DSACK0 PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DAT...

Page 363: ...C V 22 00 BSC V1 11 00 BSC Y 0 25 REF Z 1 00 REF AA 0 09 0 16 q 0 q 0 7 q 11 13 1 2 NOTES 1 DIMENSIONS AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMS L M N TO BE DETERMINED...

Page 364: ...ackage diagram B 2 Ordering Information Use the information in Table B 1 to specify the appropriate device when placing an order Table B 1 M68HC16 Z Series Ordering Information Shaded cells indicate p...

Page 365: ...K16Z1VPV25 60 MCK68HC16Z1VPV25 300 MCK16Z1VPV25B1 40 to 125 C 16 MHz 2 SPMCK16Z1MPV16 60 MCK68HC16Z1MPV16 300 MCK16Z1MPV16B1 20 MHz 2 SPMCK16Z1MPV20 60 MCK68HC16Z1MPV20 300 MCK16Z1MPV20B1 MC68HC16Z1 3...

Page 366: ...MC68HC16Z2VFC20 180 NA 25 MHz 2 NA 36 MC68HC16Z2VFC25 180 NA 40 to 125 C 16 MHz 2 NA 36 MC68HC16Z2MFC16 180 NA 20 MHz 2 NA 36 MC68HC16Z2MFC20 180 NA 144 Pin TQFP 40 to 85 C 16 MHz 2 NA 60 MC68HC16Z2C...

Page 367: ...SPMCM16Z2BCFC25 36 MCM16Z2BCFC25 180 MCM16Z2BCFC25B1 40 to 105 C 16 MHz 2 SPMCM16Z2BVFC16 36 MCM16Z2BVFC16 180 MCM16Z2BVFC16B1 20 MHz 2 SPMCM16Z2BVFC20 36 MCM16Z2BVFC20 180 MCM16Z2BVFC20B1 25 MHz 2 SP...

Page 368: ...MCM16Z2BVPV25 300 MCM16Z2BVPV25B1 40 to 125 C 16 MHz 2 SPMCM16Z2BMPV16 60 MCM16Z2BMPV16 300 MCM16Z2BMPV16B1 20 MHz 2 SPMCM16Z2BMPV20 60 MCM16Z2BMPV20 300 MCM16Z2BMPV20B1 MC68HC16Z3 ROM 4 MHz or 32 kHz...

Page 369: ...0 MC68HC16Z3CPV20 300 NA 25 MHz 2 NA 60 MC68HC16Z3CPV25 300 NA 40 to 105 C 16 MHz 2 NA 60 MC68HC16Z3VPV16 300 NA 20 MHz 2 NA 60 MC68HC16Z3VPV20 300 NA 25 MHz 2 NA 60 MC68HC16Z3VPV25 300 NA 40 to 125 C...

Page 370: ...M16Z3RVFC25B1 40 to 125 C 16 MHz 2 SPMCM16Z3RMFC16 36 MCM16Z3RMFC16 180 MCM16Z3RMFC16B1 20 MHz 2 SPMCM16Z3RMFC20 36 MCM16Z3RMFC20 180 MCM16Z3RMFC20B1 144 Pin TQFP 40 to 85 C 16 MHz 2 SPMCM16Z3RCPV16 6...

Page 371: ...20 36 MCK68HC16Z4CFC20 180 MCK16Z4CFC20B1 25 MHz 2 SPMCK16Z4CFC25 36 MCK68HC16Z4CFC25 180 MCK16Z4CFC25B1 40 to 105 C 16 MHz 2 SPMCK16Z4VFC16 36 MCK68HC16Z4VFC16 180 MCK16Z4VFC16B1 20 MHz 2 SPMCK16Z4VF...

Page 372: ...6Z4VPV25 300 MCK16Z4VPV25B1 40 to 125 C 16 MHz 2 SPMCK16Z4MPV16 60 MCK68HC16Z4MPV16 300 MCK16Z4MPV16B1 20 MHz 2 SPMCK16Z4MPV20 60 MCK68HC16Z4MPV20 300 MCK16Z4MPV20B1 2 7 V 132 Pin PQFP 40 to 85 C 16 M...

Page 373: ...nctionality with re gard to a particular MCU or MCU family The many MPBs and PPBs available let the MMDS emulate a variety of different MCUs Contact your Freescale sales representa tive who will assis...

Page 374: ...d mode operation for detailed operation from a personal computer platform without an on board monitor Integrated assembly editing evaluation programming environment for easy de velopment As many as se...

Page 375: ...FFFF when MM 1 register addresses range from FFF000 to FFFFFF With the CPU16 ADDR 23 20 follow the logic state of ADDR19 unless driven exter nally MM corresponds to IMB ADDR23 If it is cleared the SIM...

Page 376: ...STER Z SK SP STACK POINTER SP PK PC PROGRAM COUNTER PC CCR PK CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK EK XK YK ZK ADDRESS EXTENSION REGISTER K SK STACK EXTENSION FIELD SK MAC MULTIPLIER REGI...

Page 377: ...is set under the following conditions When all bits are zero in the operand of a read operation When all bits are zero in the result of a logic or arithmetic operation V Overflow Flag Set when two s...

Page 378: ...FPAR YFFA20 Not Used System Protection Control Register SYPCR YFFA22 Periodic Interrupt Control Register PICR YFFA24 Periodic Interrupt Timer Register PITR YFFA26 Not Used Software Watchdog Service Re...

Page 379: ...p Select Base Address Register 6 CSBAR6 YFFA66 Chip Select Option Address Register 6 CSOR6 YFFA68 Chip Select Base Address Register 7 CSBAR7 YFFA6A Chip Select Option Address Register 7 CSOR7 YFFA6C C...

Page 380: ...ing internal transfer op erations A show cycle allows internal transfers to be monitored externally Table D 3 indicates whether show cycle data is driven externally and whether exter nal bus arbitrati...

Page 381: ...ion D 2 2 System Integration Test Register SIMTR System Integration Test Register YFFA02 Used for factory test only D 2 3 Clock Synthesizer Control Register This register determines system clock opera...

Page 382: ...lock status until after the user first writes to SYNCR STSIM Stop Mode SIM Clock 0 When LPSTOP is executed the SIM clock is driven from the external crystal oscillator and the VCO is turned off to con...

Page 383: ...bit is driven out on the pin A read of this data register returns the value at the pin only if the pin is config ured as a discrete input Otherwise the value read is the value stored in the register...

Page 384: ...e accessed in two locations and can be read or written at any time A write to this register is stored in an internal data latch and if any pin in the corre PEPAR Port E Pin Assignment YFFA16 15 8 7 6...

Page 385: ...always read zero D 2 11 Port F Pin Assignment Register This register determines the function of port F pins Setting a bit assigns the corre sponding pin to a control signal clearing a bit assigns the...

Page 386: ...et SWT 1 0 Software Watchdog Timing This field selects the divide ratio used to establish the software watchdog time out pe riod Refer to Table D 6 The following equation calculates the time out perio...

Page 387: ...for the periodic interrupt timer PIT Bits 10 0 can be read or written at any time Bits 15 11 are unimplemented and al ways read zero PIRQL 2 0 Periodic Interrupt Request Level This field determines th...

Page 388: ...uations to calcu late timer period The following equation calculates the PIT period when a slow reference frequency is used The following equation calculates the PIT period when a fast reference frequ...

Page 389: ...Chip select pin assignment registers configure the chip select pins for discrete I O an alternate function or as an 8 bit or 16 bit chip select The possible encodings for each 2 bit field in CSPAR 0...

Page 390: ...nts including alternate functions that can be enabled by data bus mode selection during reset Table D 8 Pin Assignment Field Encoding CSxPA 1 0 Description 00 Discrete output1 NOTES 1 Does not apply t...

Page 391: ...able D 11 Reset Pin Function of CS 10 6 Data Bus Pins at Reset Chip Select Address Bus Pin Function DATA7 DATA6 DATA5 DATA4 DATA3 CS10 ADDR23 CS9 ADDR22 CS8 ADDR21 CS7 ADDR20 CS6 ADDR19 1 1 1 1 1 CS10...

Page 392: ...block that is enabled by the chip select Table D 12 shows bit encoding for the base address registers block size field D 2 20 Chip Select Option Register Boot D 2 21 Chip Select Option Registers Tabl...

Page 393: ...it controls the timing for assertion of a chip select in asynchronous mode only Selecting address strobe causes the chip select to be asserted synchronized with ad dress strobe Selecting data strobe c...

Page 394: ...increase system power consumption Table D 15 DSACK Field Encoding DSACK 3 0 Clock Cycles Required Per Access Wait States Inserted Per Access 0000 3 0 0001 4 1 0010 5 2 0011 6 3 0100 7 4 0101 8 5 0110...

Page 395: ...L 2 0 field encoding AVEC Autovector Enable This field selects one of two methods of acquiring an interrupt vector during an inter rupt acknowledge cycle This field is not applicable when SPACE 1 0 00...

Page 396: ...e Shift Count YFFA34 Used for factory test only D 2 24 Test Module Repetition Count Register TSTRC Test Module Repetition Count YFFA36 Used for factory test only D 2 25 Test Module Control Register CR...

Page 397: ...RASP field limits access to the SRAM array in microcontrollers that support sep arate user and supervisor operating modes RASP1 has no effect because the CPU16 operates in supervisor mode only This bi...

Page 398: ...ray Base Address Register High Z1 Z2 Z3 and Z4 YFFB04 15 8 7 6 5 4 3 2 1 0 NOT USED ADDR 23 ADDR 22 ADDR 21 ADDR 20 ADDR 19 ADDR 18 ADDR 17 ADDR 16 RESET 0 0 0 0 0 0 0 0 RAMBAL Array Base Address Regi...

Page 399: ...s in low power stop mode The ROM array cannot be read in this mode This bit may be read or written at any time Table D 21 MRM Address Map Address 15 0 YFF820 Masked ROM Module Configuration Register M...

Page 400: ...to the ROM array are forced external allowing memory selected by the CSM pin to respond to the access Because the MC68HC16Z2 and the MC68HC16Z3 do not support ROM emulation mode this bit should never...

Page 401: ...specified mask programmed signature pattern A user specified signature algorithm provides the capability to verify ROM array contents ROMBAH ROM Array Base Address Register High YFF824 15 14 13 12 11...

Page 402: ...e MC68HC16Z2 and MC68HC16Z3 is masked with customer specific code ROMBS 0 3 respond to system addresses 00000 to 00006 during the reset vector fetch if BOOT 0 ROMBS0 ROM Bootstrap Word 0 YFF830 15 14...

Page 403: ...RJURR6 YFF71E Right Justified Unsigned Result Register 7 RJURR7 YFF720 Left Justified Signed Result Register 0 LJSRR0 YFF722 Left Justified Signed Result Register 1 LJSRR1 YFF724 Left Justified Signed...

Page 404: ...the device is placed in background debug mode Refer to Table D 25 SUPV Supervisor Unrestricted This bit has no effect because the CPU16 always operates in supervisor mode D 5 2 ADC Test Register ADCT...

Page 405: ...two ADC clocks Transfer time is fixed at two ADC clocks Resolution time is fixed at ten ADC clocks for an 8 bit con version and twelve ADC clocks for a 10 bit conversion Final sample time is deter min...

Page 406: ...of four or eight channels selected by CD CA Length of conversion sequence s is determined by S8CM S8CM Select Eight Conversion Sequence Mode 0 Four conversion sequence 1 Eight conversion sequence Thi...

Page 407: ...Table D 28 ADC Conversion Mode SCAN MULT S8CM MODE 0 0 0 Single 4 Conversion Single Channel Sequence 0 0 1 Single 8 Conversion Single Channel Sequence 0 1 0 Single 4 Conversion Multichannel Sequence 0...

Page 408: ...0 Reserved RSLT 0 3 0 1 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 VRH RSLT 0 3 0 1 1 0 1 VRL RSLT 0 3 0 1 1 1 0 VRH VRL 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 0 0 AN0 RSLT 0 7 1 0 0 0 1 AN1 RSLT 0...

Page 409: ...0 AN5 RSLT1 AN6 RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLT0 Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X VRH RSLT0 VRL RSLT1 VRH VRL 2 RSLT2 Test Reserved RSLT3 1 0 X X X AN0 RSLT0 AN1 RSLT1 AN...

Page 410: ...gned Result Register Conversion result is unsigned right justified data Bits 9 0 are used for 10 bit resolu tion For 8 bit conversions bits 7 0 contain data and bits 9 8 are zero Bits 15 10 always ret...

Page 411: ...esolu tion For 8 bit conversions bits 15 8 contain data and bits 7 6 are zero Bits 5 0 al ways return zero when read LJURR Left Justified Unsigned Result Register YFF730 YFF73F 15 14 13 12 11 10 9 8 7...

Page 412: ...CR1 YFFC0C SCI Status Register SCSR YFFC0E SCI Data Register SCDR YFFC10 Not Used YFFC12 Not Used YFFC14 Not Used Port QS Data Register PORTQS YFFC16 Port QS Pin Assignment Register PQSPAR Port QS Dat...

Page 413: ...estricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode Bits 6 4 Not Implemented IARB 3 0 Interrupt Arbitration ID The IARB field is used to arbitrate between si...

Page 414: ...g an interrupt acknowledge cycle is supplied by the QSM INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI interrupt A write to INTV0 has no effect Reads of INTV...

Page 415: ...CCR1 bits during a transfer operation disrupts operation Bit 15 Not Implemented LOOPS Loop Mode 0 Normal SCI operation no looping feedback path disabled 1 Test SCI operation looping feedback path enab...

Page 416: ...mit Complete Interrupt Enable 0 SCI TC interrupts disabled 1 SCI TC interrupts enabled RIE Receiver Interrupt Enable 0 SCI RDRF and OR interrupts disabled 1 SCI RDRF and OR interrupts enabled ILIE Idl...

Page 417: ...15 9 Not implemented TDRE Transmit Data Register Empty 0 Transmit data register still contains data to be sent to the transmit serial shifter 1 A new character can now be written to the transmit data...

Page 418: ...red to the transmit serial shifter where addi tional format bits are added before transmission R 7 0 T 7 0 contain either the first eight data bits received when SCDR is read or the first eight data b...

Page 419: ...egister YFFC16 DDRQS PORT QS Data Direction Register YFFC17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PQSPA6 PQSPA5 PQSPA4 PQSPA3 NOT USED PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1...

Page 420: ...a output from QSPI Slave 0 Serial data input to QSPI 1 Disables data input SCK1 NOTES 1 PQS2 is a digital I O pin unless the SPI is enabled SPE set in SPCR1 in which case it becomes the QSPI serial cl...

Page 421: ...f SCK is logic zero 1 The inactive state of SCK is logic one CPOL is used to determine the inactive state of the serial clock SCK It is used with CPHA to produce a desired clock data relationship betw...

Page 422: ...I Control Register 1 SPCR1 enables the QSPI and specifies transfer delays SPCR1 must be written last during initialization because it contains SPE Writing a new value to SPCR1 while the QSPI is enable...

Page 423: ...tion is used to calculate the delay where DTL is in the range of one to 255 A zero value for DTL 7 0 causes a delay after transfer value of 8192 fsys If DT is zero in a command RAM byte a standard del...

Page 424: ...e address Bits 7 4 Not Implemented NEWQP 3 0 New Queue Pointer Value This field contains the first QSPI queue address D 6 13 QSPI Control Register 3 SPCR3 contains the loop mode enable bit halt and mo...

Page 425: ...put pin is negated by an external driver HALTA Halt Acknowledge Flag 0 QSPI is not halted 1 QSPI is halted HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit Bit 4 Not Implemen...

Page 426: ...in command RAM Command RAM consists of 16 bytes Each byte is divided into two fields The periph eral chip select field enables peripherals for transfer The command control field pro vides transfer opt...

Page 427: ...select bits to select one or more external devices for serial data transfers More than one peripheral chip select may be activated at a time and more than one peripheral chip can be connected to each...

Page 428: ...Not Used YFFC08 Not Used MCCI Pin Assignment Register MPAR YFFC0A Not Used MCCI Data Direction Register MDDR YFFC0C Not Used MCCI Port Data Register PORTMC YFFC0E Not Used MCCI Port Pin State Registe...

Page 429: ...tration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority Each module that can generate interrupt requests must be assigned a unique non zero IARB fie...

Page 430: ...ammed by the user INTV 1 0 Interrupt Vector Source INTV 1 0 are the two low order bits of the three interrupt vectors for the MCCI They are automatically set by the MCCI to indicate the source of the...

Page 431: ...SCK is determined by the SPI enable bit in SPCR1 Clearing a bit in MPAR assigns the corresponding pin to general purpose I O setting a bit assigns the pin to the SPI Refer to Table D 39 Bits 15 8 7 4...

Page 432: ...to SPI 1 Disables data input SCK1 NOTES 1 SCK is automatically assigned to the SPI whenever the SPI is enabled when the SPE bit in the SPCR1 is set Master DDR2 Clock output from SPI Slave Clock input...

Page 433: ...s of PORTMCP always return the state of the pins regardless of whether the pins are configured for input or output Writes to PORTMCP have no effect D 7 9 SCI Control Register 0 SCCR0 contains the SCI...

Page 434: ...es Changing the value of SCCR1 bits during a transfer operation can disrupt the transfer Table D 41 Examples of SCI Baud Rates Nominal Baud Rate Actual Baud Rate Percent Error Value of SCBR 500 00 00...

Page 435: ...tect start count on first one after stop bit s PT Parity Type 0 Even parity 1 Odd parity PE Parity Enable 0 SCI parity disabled 1 SCI parity enabled M Mode Select 0 10 bit SCI frame 1 start bit 8 data...

Page 436: ...g SCDR the newly set status bit is not cleared SCSR must be read again with the bit set and SCDR must be read or written before the status bit is cleared A long word read can consecutively access both...

Page 437: ...r detected in the received data D 7 12 SCI Data Register SCDR consists of two data registers located at the same address The receive data register RDR is a read only register that contains data receiv...

Page 438: ...ogic level one CPOL is used to determine the inactive state of the serial clock SCK It is used with CPHA to produce a desired clock data relationship between master and slave devices CPHA Clock Phase...

Page 439: ...ission Only the SPI can set bits in SPSR The CPU16 reads SPSR to obtain SPI status information and writes it to clear status flags SPIF SPI Finished Flag 0 SPI is not finished 1 SPI is finished WCOL W...

Page 440: ...te contains the most significant eight bits of the transmitted or received data Bit 15 of the SPDR is the MSB of the 16 bit data LOWB Lower Byte In 8 bit transfer mode the lower byte contains the tran...

Page 441: ...Register 3 TIC3 YFF914 Timer Output Compare Register 1 TOC1 YFF916 Timer Output Compare Register 2 TOC2 YFF918 Timer Output Compare Register 3 TOC3 YFF91A Timer Output Compare Register 4 TOC4 YFF91C...

Page 442: ...en simultaneous interrupt requests of the same priority Each module that can generate interrupt requests must be assigned a unique non zero IARB field value D 8 2 GPT Test Register GPTMTR GPT Module T...

Page 443: ...urces Name Source Number Source Vector Number 0000 Adjusted Channel IVBA 0000 IC1 0001 Input Capture 1 IVBA 0001 IC2 0010 Input Capture 2 IVBA 0010 IC3 0011 Input Capture 3 IVBA 0011 OC1 0100 Output C...

Page 444: ...se Accumulator Control Register Counter PACTL enables the pulse accumulator and selects either event counting or gated mode In event counting mode PACNT is incremented each time an event occurs In gat...

Page 445: ...8 9 Output Compare Registers 1 4 TOC 1 4 Output Compare Registers 1 4 YFF914 YFF91A The output compare registers are 16 bit read write registers which can be used as out put waveform controls or as el...

Page 446: ...input capture Refer to Table D 47 D 8 12 Timer Interrupt Mask Registers 1 and 2 TCTL1 TCTL2 Timer Control Registers 1 2 YFF91E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OM5 OL5 OM4 OL4 OM3 OL3 OM2 OL2 EDG...

Page 447: ...pt disabled 1 Interrupt requested when TOF flag is set PAOVI Pulse Accumulator Overflow Interrupt Enable 0 Pulse accumulator overflow interrupt disabled 1 Interrupt requested when PAOVF flag is set PA...

Page 448: ...This flag is set each time TCNT advances from a value of FFFF to 0000 PAOVF Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of FF to 00 P...

Page 449: ...1 Clock selected by PPR 2 0 is driven out PWMA pin PPR 2 0 PWM Prescaler PCLK Select This field selects one of seven prescaler taps or PCLK to be PWMCNT input Refer to Table D 49 SFA PWMA Slow Fast Se...

Page 450: ...read only registers at the end of each duty cycle Re set state is 0000 Table D 50 PWM Frequency Ranges PPR 2 0 Prescaler Tap SFA B 0 SFA B 1 16 78 MHz 20 97 MHz 25 17 MHz 16 78 MHz 20 97 MHz 25 17 MHz...

Page 451: ...from bits 8 0 at this address Bits 15 9 always read as zeros Reset state is 0000 PRESCL GPT Prescaler YFF92C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNUSED POWER ON RESET ONLY 0 0 0 0 0 0 0 0 0 Freesca...

Page 452: ...REGISTER SUMMARY M68HC16 Z SERIES D 78 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 453: ...isters equated to their memory address This allows programmers to use the register name in their programs and then the assembler selects the correct memory address for that register ORG00000 ASM This...

Page 454: ...IBUTED REGISTER CSPDR EQU FA41 PORT C DATA REGISTER CSPAR0 EQU FA44 CHIP SELECT PIN ASSIGNMENT REGISTER 0 CSPAR1 EQU FA46 CHIP SELECT PIN ASSIGNMENT REGISTER 1 CSBARBT EQU FA48 CHIP SELECT BOOT BASE A...

Page 455: ...1 SCSR EQU FC0C SCI STATUS REGISTER SCDR EQU FC0E SCI DATA REGISTER FULL WORD NOT LAST 8 BITS QPDR EQU FC15 QSM PORT DATA REGISTER QPAR EQU FC16 QSM PIN ASSIGNMENT REGISTER QDDR EQU FC17 QSM DATA DIRE...

Page 456: ...PT VECTOR REGISTER ILSPI EQU FC06 SPI INTERRUPT LEVEL REGISTER MPAR EQU FC09 MCCI PIN ASSIGNMENT REGISTER MDDR EQU FC0B MCCI DATA DIRECTION REGISTER PORTMC EQU FC0D MCCI PORT DATA REGISTER PORTMCP EQU...

Page 457: ...RR0 EQU F710 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 0 RJURR1 EQU F712 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 1 RJURR2 EQU F714 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 2 RJURR3 EQU F716 RIGHT JUST...

Page 458: ...g mode or some other appropriate routine ORG 0008 put the following code in memory starting at address 0008 of the map after the reset vector there is a total of 252 of these DC W BDM lines Vector Num...

Page 459: ...gned Reserved DC W BDM 50 Unassigned Reserved DC W BDM 51 Unassigned Reserved DC W BDM 52 Unassigned Reserved DC W BDM 53 Unassigned Reserved DC W BDM 54 Unassigned Reserved DC W BDM 55 Unassigned Res...

Page 460: ...W BDM 102 User Defined Interrupt Vector 47 DC W BDM 103 User Defined Interrupt Vector 48 DC W BDM 104 User Defined Interrupt Vector 49 DC W BDM 105 User Defined Interrupt Vector 50 DC W BDM 106 User...

Page 461: ...BDM 157 User Defined Interrupt Vector 102 DC W BDM 158 User Defined Interrupt Vector 103 DC W BDM 159 User Defined Interrupt Vector 104 DC W BDM 160 User Defined Interrupt Vector 105 DC W BDM 161 Use...

Page 462: ...ctor 156 DC W BDM 212 User Defined Interrupt Vector 157 DC W BDM 213 User Defined Interrupt Vector 158 DC W BDM 214 User Defined Interrupt Vector 159 DC W BDM 215 User Defined Interrupt Vector 160 DC...

Page 463: ...Title INITSYS Description Initialize configure system including the Software Watchdog and System Clock INITSYS give initial values for extension registers and initialize system clock and COP LDAB 0F...

Page 464: ...16Z1EVB evaluation board Refer to the M68HC16Z1EVB Evaluation Board User s Manual M68HC16Z1EVB D for further in formation NOTE These programs will also work on the modular evaluation board MEVB using...

Page 465: ...Port F data register Port E will be incremented each loop The hardwire of the M68HC16Z1EVB is from DSACK0 to MODCLK from DSACK1 to IRQ1 and from AVEC to IRQ2 The numbers start at 00 and go to 07 INCLU...

Page 466: ...ait states The DSACK field of the Chip Select Option Registers may need to be adjusted for chips that have faster or slower access times INCLUDE EQUATES ASM table of EQUates for common register addres...

Page 467: ...ncrement Z index register to next word CMPA 00 BEQ PRINT end xloop if the end of the string 00 is CMPB 00 detected in either accumulator A or B BNE XLOOP PRINT This loop reads its string from the U1 a...

Page 468: ...rnate between a frequency of 16 78MHz and 4 194MHz Note that because we are writing to the screen we also need to correct the BAUD rate 1200 each time we change the frequency Make sure that your termi...

Page 469: ...oop counter BNE LOOP1 loop 5 times LDAB 4F change clock frequency to 4 194MHz STAB SYNCR w 0 x 1 y 001111 LOOP2 BRCLR SYNCR 1 8 LOOP2 wait until synthesizer lock bit is set LDD 006D STD SCCR0 set BAUD...

Page 470: ...unning at 4 194 MHz 0a 0d 00 Interrupts Exceptions BDM BGND exception vectors point here and put the user into background debug mode E 2 1 4 Example 4 Software Watchdog Periodic Interrupt and Autovect...

Page 471: ...RAM ASM turn on internal SRAM at 10000 set stack in bank 1 SK 1 SP 03FE INCLUDE INITSCI ASM set SCI baud rate at 9600 baud enable SCI transmitter and receiver LDD 0638 STD PICR set the periodic interr...

Page 472: ...outine to send out one byte to SCI LDAA SCSR read SCI status reg to check clear TDRE bit ANDA 01 check only the TDRE flag bit BEQ SEND_CH if TDR is not empty go back to check it again LDAA 00 clear A...

Page 473: ...DDA 01 increment of hours DAA decimal adjust A STD HRCNT Z store new of hours CMPA 24 compare of hours to 24 BNE RETURN if of hours 24 then display new time CLR HRCNT Z if of hours 24 then clear of ho...

Page 474: ...number BRA PRTLSB PRTMSB LSRB shift high 4 bits down to low 4 bits position LSRB LSRB LSRB PRTLSB the actual conversion process ADDB 30 add 30 to the hex number CMPB 39 check for digithood BLS NOTAF...

Page 475: ...00008 ASM initialize interrupt vectors ORG 0200 start program after interrupt vectors Initialization Routines INCLUDE INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 set sys clock at 16 78MHz disable CO...

Page 476: ...G00008 ASM initialize interrupt vectors ORG 0200 start program after exception vector table Initialize INIT INCLUDE INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 set sys clock at 16 78 MHz disable COP...

Page 477: ...t until TC is set RTS finish sending out byte STRING DC I AM A HAPPY EVB16 RUNNING YOUR CODE 0A 0D 00 Interrupts Exceptions BDM BGND exception vectors point here and put the user in background debug m...

Page 478: ...C W BDM Output Compare 4 DC W BDM Input Capture 4 Output Compare 5 DC W BDM Timer Overflow DC W BDM Pulse Accumulator Overflow elevated DC W BDM Pulse Accumulator Input ORG 0200 start program after in...

Page 479: ...LDAB 00 TBXK set XK to bank 0 for STRING access PAOV_CNT EQU 0 counter variable for PAOV_ROUTINE LDAB 01 TBZK LDZ 0000 PAOV_CNT will be indexed off ZK IZ LDAB 0A STAB PAOV_CNT Z load a 10 into the va...

Page 480: ...ote that every one of the GPT interrupt service routines clears its flag bit at the end of the routine before the RTI instruction EVEN IC1_ROUTINE execute when IC1 senses a transition LDX STRING_IC1 J...

Page 481: ...ING_PAOV JSR SEND_STRING print the message LDAB 0A STAB PAOV_CNT Z reload the counter so we can do it again PAOV_DONE BCLR TFLG2 20 clear the PAOV flag bit RTI all done BDM BGND all other exception ve...

Page 482: ...INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 30 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 483: ...tified signed LJSRR D 36 unsigned LJURR D 37 module configuration register ADCMCR 8 3 D 30 port ADA data register PORTADA D 30 result registers 8 13 right justified unsigned RJURR D 36 status register...

Page 484: ...7 1 BR 5 46 5 49 5 54 5 64 5 65 Break frame 9 25 10 17 Breakpoint acknowledge cycle 5 41 exceptions 4 40 hardware breakpoints 5 41 mode selection 5 52 operation 5 42 Breakpoints 4 41 Buffer amplifier...

Page 485: ...nel conversions 8 11 parameters 8 8 single channel conversions 8 10 counter CCTR D 36 timing 8 12 CPHA 9 17 10 8 10 9 10 10 D 47 CPOL 9 17 10 8 D 47 CPR D 73 CPROUT 11 10 D 73 CPTQP 9 8 D 51 CPU space...

Page 486: ...DSCK D 53 DSCKL D 49 DSCLK 4 44 5 53 DSI 5 53 DSO 5 53 DSP 4 45 DT D 53 DTL D 49 Dynamic bus sizing 5 33 E EBI 5 60 ECLK 5 21 bus timing 16 78 MHz A 41 20 97 MHz A 42 25 17 MHz A 43 low voltage A 40 o...

Page 487: ...mulation mode 11 15 General purpose timer GPT See GPT 11 1 GPT address map D 67 block diagram 11 2 capture compare unit 11 10 block diagram 11 11 features 3 2 general information 11 1 purpose I O 11 8...

Page 488: ...5 59 11 8 I I4 O5 11 14 D 71 D 73 I4 O5F D 74 IARB GPT 11 6 D 68 MCCI 10 3 D 55 QSM 9 3 D 39 SIM 5 3 5 59 D 7 IC4 11 14 ICD16 ICD32 C 2 ICF D 74 ICI D 73 ICR D 68 IDD 5 54 IDLE 9 29 10 21 D 43 D 63 Id...

Page 489: ...l sensitivity 5 58 LJSRR D 36 LJURR D 37 LOC D 8 LOCK 7 3 D 26 Lock registers LOCK D 26 Logic analyzer pod connectors C 2 levels definition 2 6 Loop mode LOOPS D 41 D 61 LOOPQ D 50 LOOPS D 41 D 61 Los...

Page 490: ...B C 2 pin characteristics 3 11 power connections 3 13 signal characteristics 3 13 function 3 15 MDDR 10 2 10 4 Mechanical data and ordering information B 1 Memory maps combined program and data MC68HC...

Page 491: ...n 11 14 flags OCF D 74 functions 11 13 11 14 interrupt enable OCI bit D 73 mode bits output compare level bits OM OL D 72 status flag OCxF bit 11 13 Overflow flag V 4 4 D 3 Overrun error OR D 43 D 63...

Page 492: ...es 4 36 Programming examples E 12 CPU16 E 23 GPT E 25 QSM SCI E 24 SIM E 13 PROUT 11 10 PRS D 31 PRU C 2 PSHM 4 9 PT 9 26 10 19 D 42 D 61 PTP D 14 PULM 4 9 Pulse accumulator 11 1 block diagram 11 15 c...

Page 493: ...ters 9 6 control registers 9 6 status register 9 7 timing A 46 master CPHA 0 CPHA 1 A 47 slave CPHA 0 CPHA 1 A 48 low voltage A 45 QTEST 9 2 D 39 Queue pointers completed queue pointer CPTQP 9 8 end q...

Page 494: ...diagram MCCI 10 15 QSM 9 23 operation 9 28 10 20 wakeup 9 29 10 22 registers 9 24 control register 0 MCCI SCCR0A B 10 13 D 59 control register 1 MCCI SCCR1A B 10 16 D 60 control registers QSM SCCR 9 2...

Page 495: ...CREG D 22 distributed register DREG D 22 repetition count register TSTRC D 22 shift count register TSTSC D 22 reset 5 48 state of pins 5 54 software watchdog 5 25 block diagram with PIT 5 25 spurious...

Page 496: ...ter SAR 8 13 Supervisor unrestricted data space SUPV ADC D 30 GPT D 68 MCCI 10 3 D 55 QSM D 39 SIM 5 3 D 6 SUPV 10 3 D 6 D 30 D 39 D 55 D 68 SW D 8 SWE 5 25 D 12 SWP 5 26 D 12 SWSR D 15 SWT 5 26 D 12...

Page 497: ...O 5 6 frequency fVCO 5 6 frequency ramp time 5 56 limiting diodes 8 19 VPP C 2 VRH 5 53 8 1 8 3 8 14 8 23 VRL 5 53 8 1 8 3 8 14 8 23 VSRC 8 22 VSSA 8 1 8 3 8 14 VSTBY 6 2 W W D 8 WAIT 7 3 D 26 Wait st...

Page 498: ...M68HC16 Z SERIES I 16 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 499: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 500: ...uctor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer...

Page 501: ...ributor Click to View Pricing Inventory Delivery Lifecycle Information NXP MC68CK16Z1CAG16 MC68HC16Z1CAG16 MC68HC16Z1CAG20 MC68HC16Z1CAG25 MC68HC16Z1CEH16 MC68HC16Z1CEH20 MC68HC16Z1CEH25 MC68HC16Z1MAG...

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