ANALOG-TO-DIGITAL CONVERTER
M68HC16 Z SERIES
8-14
USER’S MANUAL
Refer to
for register mapping and configuration.
8.8 Pin Considerations
The ADC requires accurate, noise-free input signals for proper operation. The follow-
ing sections discuss the design of external circuitry to maximize ADC performance.
8.8.1 Analog Reference Pins
No A/D converter can be more accurate than its analog reference. Any noise in the
reference can result in at least that much error in a conversion. The reference for the
ADC, supplied by pins V
RH
and V
RL
, should be low-pass filtered from its source to ob-
tain a noise-free, clean signal. In many cases, simple capacitive bypassing may suf-
fice. In extreme cases, inductors or ferrite beads may be necessary if noise or RF
energy is present. Series resistance is not advisable since there is an effective DC cur-
rent requirement from the reference voltage by the internal resistor string in the RC
DAC array. External resistance may introduce error in this architecture under certain
conditions. Any series devices in the filter network should contain a minimum amount
of DC resistance.
For accurate conversion results, the analog reference voltages must be within the lim-
its defined by V
DDA
and V
SSA
, as explained in the following subsection.
8.8.2 Analog Power Pins
The analog supply pins (V
DDA
and V
SSA
) define the limits of the analog reference volt-
ages (V
RH
and V
RL
) and of the analog multiplexer inputs.
is a diagram of
the analog input circuitry.
Table 8-9 Result Register Formats
Result Data Format
Description
Unsigned
right-justified format
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution,
bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero
when read.
Signed
left-justified format
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution, bits
[15:8] are used for 8-bit conversion (bits [7:6] are zero). Although the ADC is unipolar, it
is assumed that the zero point is (VRH – VRL) / 2 when this format is used. The value read
from the register is an offset two’s-complement number; for positive input, bit 15 equals
zero, for negative input, bit 15 equals one. Bits [5:0] always return zero when read.
Unsigned
left-justified format
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution,
bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). Bits [5:0] always return zero
when read.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
