M68HC16 Z SERIES
SYSTEM INTEGRATION MODULE
USER’S MANUAL
5-55
5.7.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven to guarantee this length of reset to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts the RESET
pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512
cycles, the control logic continues to assert the RESET pin until the internal reset sig-
nal is negated.
After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the RESET input is tested.
When the input is at logic level one, reset exception processing begins. If, however,
the RESET input is at logic level zero, reset control logic drives the pin low for another
512 cycles. At the end of this period, the pin again goes to high-impedance state for
ten cycles, then it is tested again. The process repeats until external RESET is
released.
5.7.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of the system and the clock syn-
thesizer power. Regardless of clock source, voltage must be applied to clock synthe-
sizer power input pin V
DDSYN
for the MCU to operate. The following discussion
assumes that V
DDSYN
is applied before and during reset, which minimizes crystal
start-up time. When V
DDSYN
is applied at power-on, start-up time is affected by spe-
cific crystal parameters and by oscillator circuit design. V
DD
ramp-up time also affects
pin state during reset. Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS
for
voltage and timing specifications.
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The power-on reset circuit releases the internal re-
set line as V
DD
ramps up to the minimum operating voltage, and SIM pins are initial-
ized to the values shown in
. When V
DD
reaches the minimum operating
voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to
specified limp mode frequency (f
limp
). The external RESET line remains asserted until
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
NOTE
V
DDSYN
and all V
DD
pins must be powered. Applying power to
V
DDSYN
only will cause errant behavior of the MCU.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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