UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
96 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.6.16 ADC clock source select register
The ADCCLKSEL register selects the ADC clock, which can be the FRO or sys_pll.
8.6.17 ADC clock divider register
The ADCCLKDIV register controls how the ADC clock is divided to provide the ADC clock
to the ADC controller. The ADC clock can be shut down completely by setting the DIV field
to zero.
8.6.18 SCT clock source select register
The SCTCLKSEL register selects the SCT clock, which can be the FRO, main clock or
sys_pll.
8.6.19 SCT clock divider register
The SCTCLKDIV register controls how the SCT clock is divided to provide the SCT clock
to the SCT module. The SCT clock can be shut down completely by setting the DIV field
to zero.
Table 141. ADC clock source select register (ADCCLKSEL, address 0x4004 8064) bit
description
Bit
Symbol
Value
Description
Reset value
1:0
SEL
Clock source for ADC clock.
0x0
0x0
FRO
0x1
SYS PLL
0x2
None
0x3
None
31:3
-
Reserved
-
Table 142. ADC clock divider register (ADCCLKDIV, address 0x4004 8068) bit description
Bit
Symbol
Value
Description
Reset value
7:0
DIV
ADC clock divider values.
0: ADC clock disabled.
1: Divide by 1.
…
255: Divide by 255.
0x0
31:8
-
Reserved
-
Table 143. SCT clock source select register (SCTCLKSEL, address 0x4004 806C) bit
description
Bit
Symbol
Value
Description
Reset value
1:0
SEL
Clock source for SCT clock
0x0
0x0
FRO
0x1
Main clock
0x2
SYS PLL
0x3
None
31:2
-
Reserved
-
