UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
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7.1 How to read this chapter
The NVIC is identical on all LPC84x parts.
7.2 Features
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
•
Tightly coupled interrupt controller provides low interrupt latency.
•
Controls system exceptions and peripheral interrupts.
•
The NVIC supports 32 vectored interrupts.
•
Four programmable interrupt priority levels with hardware priority level masking.
•
Software interrupt generation using the ARM exceptions SVCall and PendSV (see
•
Support for NMI.
•
ARM Cortex M0+ Vector table offset register VTOR implemented.
7.3 General description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.3.1 Interrupt sources
lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. Interrupts with the same priority level are
serviced in the order of their interrupt number.
See
for a detailed description of the NVIC and the NVIC register description.
UM11029
Chapter 7: LPC84x Nested Vectored Interrupt Controller
(NVIC)
Rev. 1.0 — 16 June 2017
User manual
Table 108. Connection of interrupt sources to the NVIC
Interrupt
number
Name
Description
Flags
0
SPI0_IRQ
SPI0 interrupt
Table 340 “SPI Interrupt Enable read and Set
register (INTENSET, addresses 0x4005 800C (SPI0),
0x4005 C00C (SPI1)) bit description”
1
SPI1_IRQ
SPI1 interrupt
Same as SPI0_IRQ
2
DAC0_IRQ
DAC0 interrupt
-
