UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
387 of 515
NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT. (Other bits can be
written in a subsequent write after HALT is set to 1.)
Remark:
If CLKMODE = 0x3 is selected, wait at least 12 system clock cycles between a
write access to the H, L or unified version of this register and the next write access. This
restriction does not apply when writing to the HALT bit or bits and then writing to the CTRL
register again to restart the counters - for example because software must update the
MATCH register, which is only allowed when the counters are halted.
Remark:
If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
Table 387. SCTimer/PWM control register (CTRL, offset 0x004) bit description
Bit
Symbol
Value
Description
Reset
value
0
DOWN_L
-
This read-only bit is 1 when the L or unified counter is counting down. Hardware sets
this bit when the counter is counting up, counter limit occurs, and BIDIR =
1.Hardware clears this bit when the counter is counting down and a limit condition
occurs or when the counter reaches 0.
0
1
STOP_L
-
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
related to the counter can occur. If a designated start event occurs, this bit is cleared
and counting resumes.
0
2
HALT_L
-
When this bit is 1, the L or unified counter does not run and no events can occur. A
reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is
possible to remove the halt condition while keeping the SCTimer/PWM in the stop
condition (not running) with a single write to this register to simultaneously clear the
HALT bit and set the STOP bit.
Remark:
Once set, only software can clear this bit to restore counter operation. This
bit is set on reset.
1
3
CLRCTR_L -
When the counter is halted (not just stopped), writing a 1 to this bit will clear the L or
unified counter. This bit always reads as 0.
0
4
BIDIR_L
L or unified counter direction select
0
0
Up. The counter counts up to a limit condition, then is cleared to zero.
1
Up-down. The counter counts up to a limit, then counts down to a limit condition or to
0.
12:5
PRE_L
-
Specifies the factor by which the SCTimer/PWM clock is prescaled to produce the L
or unified counter clock. The counter clock is clocked at the rate of the
SCTimer/PWM clock divided by PRE_L+1.
Remark:
Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
0
15:13
-
-
Reserved
-
16
DOWN_H
-
This read-only bit is 1 when the H counter is counting down. Hardware sets this bit
when the counter is counting, a counter limit condition occurs, and BIDIR is 1.
Hardware clears this bit when the counter is counting down and a limit condition
occurs or when the counter reaches 0.
0
17
STOP_H
-
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related
to the counter can occur. If such an event matches the mask in the Start register, this
bit is cleared and counting resumes.
0
