UM11029
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User manual
Rev. 1.0 — 16 June 2017
383 of 515
NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.1.1 Counter configuration and control registers
The SCTimer/PWM contains two registers for configuring the SCTimer/PWM and monitor
and control its operation by software.
•
The configuration register (CONFIG) configures the SCTimer/PWM in single, 32-bit
counter mode or in dual, 16-bit counter mode, configures the clocking and clock
synchronization, and configures automatic limits and the use of reload registers.
•
The control register (CTRL) allows to monitor and set the counter direction, and to
clear, start, stop, or halt the 32-bit counter or each individual 16-bit counter if in
dual-counter mode.
21.6.1.2 Event configuration registers
Each event is associated with two registers:
•
One EVn_CTRL register per event to define what triggers the event.
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One EVn_STATE register per event to enable the event.
21.6.1.3 Match and capture registers
The SCTimer/PWM includes a set of registers to store the match or capture values. Each
match register is associated with a match reload register which automatically reloads the
match register at the beginning of each counter cycle. This register group includes the
following registers:
•
One REGMODE register per match/capture register to configure each match/capture
register for either storing a match value or a capture value.
•
A set of match/capture registers with each register, depending on the setting of
REGMODE, either storing a match value or a counter value.
•
One reload register for each match register.
21.6.1.4 Event select registers for the counter operations
This group contains the registers that select the events which affect the counter. Counter
actions are limit, halt, and start or stop and apply to the unified counter or to the two 16-bit
counters. Also included is the counter register with the counter value, or values in the
dual-counter set-up. This register group includes the following registers:
•
LIMIT selects the events that limit the counter.
•
START and STOP select events that start or stop the counter.
•
HALT selects events that halt the counter: HALT
•
COUNT contains the counter value.
The LIMIT, START, STOP, and HALT registers each contain one bit per event that selects
for each event whether the event limits, stops, starts, or halts the counter, or counters in
dual-counter mode.
In the dual-counter mode, the events can be selected independently for each counter.
