NXP Semiconductors LPC84x, User Manual

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 306 of 515
18.1 How to read this chapter
The SPI interfaces are available on all parts depending on the switch matrix configuration.
18.2 Features
•
Data transmits of 1 to 16 bits supported directly. Larger frames supported by software.
•
Master and slave operation.
•
Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
•
Control information can optionally be written along with data. This allows very
versatile operation, including frames of arbitrary length.
•
Up to four Slave Select input/outputs with selectable polarity and flexible usage.
• Supports DMA transfers: SPIn transmit and receive functions can operated with the
system DMA controller.
Remark:
Texas Instruments SSI and National Microwire modes are not supported.
18.3 Basic configuration
Configure SPI0/1 using the following registers:
• In the SYSAHBCLKCTRL register, set bit 11 and 12 ( Table 146 ) to enable the clock to
the register interface.
•
Clear the SPI0/1 peripheral resets using the PRESETCTRL register ( Table 148 ).
•
Enable/disable the SPI0/1 interrupts in interrupt slots #0 and 1 in the NVIC.
• Configure the SPI0/1 pin functions through the switch matrix. See Section 18.4 .
• The peripheral clock for both SPIs is the system clock (see Figure 7 “LPC84x clock
generation” ).
UM11029
Chapter 18: LPC84x SPI0/1
Rev. 1.0 — 16 June 2017 User manual