NXP Semiconductors LPC84x, User Manual

Page: 255 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 255 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
15.7.4.3 Wake-up from sleep mode
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
15.7.5 Deep-sleep mode
In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which can be selected or deselected during deep-sleep mode in the PDSLEEPCFG
register. The main clock, and therefore all peripheral clocks, are disabled except for the
clock to the watchdog timer if the watchdog oscillator is selected. The FRO is running, but
its output is disabled. The flash is in standby mode.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
15.7.5.1 Power configuration in deep-sleep mode
Power consumption in deep-sleep mode is determined by the deep-sleep power
configuration setting in the PDSLEEPCFG (
Table 170 ) register:
•
The watchdog oscillator can be left running in deep-sleep mode if required for the
WWDT.
•
The BOD circuit can be left running in deep-sleep mode if required by the application.
15.7.5.2 Programming deep-sleep mode
The following steps must be performed to enter deep-sleep mode:
1. The PM bits in the PCON register must be set to 0x1 ( Table 291 ).
2. Select the power configuration in deep-sleep mode in the PDSLEEPCFG ( Table 170 )
register.
3. Select the power configuration after wake-up in the PDAWAKECFG ( Table 171 )
register.
4. If any of the available wake-up interrupts are needed for wake-up, enable the
interrupts in the interrupt wake-up registers ( Table 168 , Table 169 ) and in the NVIC.
5. Select the FRO as the main clock. See Table 137 .
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0+ SCR register ( Table 288 ).
7. Use the ARM WFI instruction.
15.7.5.3 Wake-up from deep-sleep mode
The microcontroller can wake up from deep-sleep mode in the following ways:
• Signal on one of the eight pin interrupts selected in Table 167 . Each pin interrupt must
also be enabled in the STARTERP0 register ( Table 168 ) and in the NVIC.
•
BOD signal, if the BOD is enabled in the PDSLEEPCFG register: