NXP Semiconductors LPC822M101JDH20, User Manual, Page: 58 / 487

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User manual Rev. 1.2 — 5 October 2016 58 of 487
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Chapter 5: LPC82x System configuration (SYSCON)
reference will be turned off, the oscillator and the phase-frequency detector will be
stopped and the dividers will enter a reset state. While in PLL Power-down mode, the lock
output will be low to indicate that the PLL is not in lock. When the PLL Power-down mode
is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal
operation and will make the lock signal high once it has regained lock on the input clock.
5.7.4.3 Divider ratio programming
5.7.4.3.1 Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in
Table 24 . This guarantees an
output clock with a 50% duty cycle.
5.7.4.3.2 Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in
Table 24 .
5.7.4.3.3 Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
5.7.4.4 Frequency selection
The PLL frequency equations use the following parameters (also see Figure 7 ):
5.7.4.4.1 Normal mode
In this mode the post divider is enabled, giving a 50% duty cycle clock with the following
frequency relations:
(1)
Table 56. PLL frequency parameters
Parameter System PLL
FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see
Section 5.6.9 ).
FCCO Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
FCLKOUT Frequency of sys_pllclkout. This is the PLL output frequency and must be
< 100 MHz.
P System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see
Section 5.6.3 ).
M System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section 5.6.3 ).
Fclkout M Fclkin

FCCO
 
2 P
   
= =