UM10800
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© NXP Semiconductors N.V. 2016. All rights reserved.
User manual
Rev. 1.2 — 5 October 2016
30 of 487
NXP Semiconductors
UM10800
Chapter 5: LPC82x System configuration (SYSCON)
5.5.2 Power control of analog components
The system control block controls the power to the analog components such as the
oscillators and PLL, the BOD, and the analog comparator. For details, see the following
registers:
Section 5.6.31 “Deep-sleep mode configuration register”
Section 5.6.3 “System PLL control register”
Section 5.6.6 “Watchdog oscillator control register”
Section 5.6.5 “System oscillator control register”
Fig 5.
Clock generation
SYSTEM PLL
watchdog oscillator
IRC oscillator
IRC oscillator
watchdog oscillator
SYSTEM
OSCILLATOR
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
system PLL clock select
CLOCK DIVIDER
SYSAHBCLKDIV
AHB clock 0
(core, system;
always-on)
CLOCK DIVIDER
UARTCLKDIV
USART0
USART1
USART2
WWDT
IRC oscillator
WKT
low-power oscillator
WKT
watchdog oscillator
IRC oscillator
system oscillator
CLOCK DIVIDER
CLKOUTDIV
CLKOUT pin
CLKOUTSEL
(CLKOUT clock select)
main clock
system clock
SYSAHBCLKCTRL[1:19]
(system clock enable)
memories
and peripherals,
peripheral clocks
19
IOCONCLKDIV
CLOCK DIVIDER
IOCON
glitch filter
7
XTALIN
CLKIN
XTALOUT
SYSCON
PMU
FRACTIONAL RATE
GENERATOR