NXP Semiconductors LPC822M101JDH20, User Manual, Page: 262 / 487

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User manual Rev. 1.2 — 5 October 2016 262 of 487
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Chapter 16: LPC82x SCTimer/PWM
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 0: Registers operate as match and reload registers.
– REGMODEn = 1: Registers operate as capture and capture control registers.
Table 222. Register overview: State Configurable Timer SCT/PWM (base address 0x5000 4000)
Name Access Address
offset
Description Reset value Reference
CONFIG R/W 0x000 SCT configuration register 0x0000 7E00 Table 223
CTRL R/W 0x004 SCT control register 0x0004 0004 Table 224
CTRL_L R/W 0x004 SCT control register low counter 16-bit 0x0004 0004 Table 224
CTRL_H R/W 0x006 SCT control register high counter 16-bit 0x0004 0004 Table 224
LIMIT R/W 0x008 SCT limit event select register 0x0000 0000 Table 225
LIMIT_L R/W 0x008 SCT limit event select register low counter 16-bit 0x0000 0000 Table 225
LIMIT_H R/W 0x00A SCT limit event select register high counter 16-bit 0x0000 0000 Table 225
HALT R/W 0x00C SCT halt events elect register 0x0000 0000 Table 226
HALT_L R/W 0x00C SCT halt event select register low counter 16-bit 0x0000 0000 Table 226
HALT_H R/W 0x00E SCT halt event select register high counter 16-bit 0x0000 0000 Table 226
STOP R/W 0x010 SCT stop event select register 0x0000 0000 Table 227
STOP_L R/W 0x010 SCT stop event select register low counter 16-bit 0x0000 0000 Table 227
STOP_H R/W 0x012 SCT stop event select register high counter 16-bit 0x0000 0000 Table 227
START R/W 0x014 SCT start event select register 0x0000 0000 Table 228
START_L R/W 0x014 SCT start event select register low counter 16-bit 0x0000 0000 Table 228
START_H R/W 0x016 SCT start event select register high counter 16-bit 0x0000 0000 Table 228
- - 0x018 - 0x03C Reserved -
COUNT R/W 0x040 SCT counter register 0x0000 0000 Table 229
COUNT_L R/W 0x040 SCT counter register low counter 16-bit 0x0000 0000 Table 229
COUNT_H R/W 0x042 SCT counter register high counter 16-bit 0x0000 0000 Table 229
STATE R/W 0x044 SCT state register 0x0000 0000 Table 230
STATE_L R/W 0x044 SCT state register low counter 16-bit 0x0000 0000 Table 230
STATE_H R/W 0x046 SCT state register high counter 16-bit 0x0000 0000 Table 230
INPUT RO 0x048 SCT input register 0x0000 0000 Table 231
REGMODE R/W 0x04C SCT match/capture mode register 0x0000 0000 Table 232
REGMODE_L R/W 0x04C SCT match/capture mode register low counter
16-bit 0x0000 0000 Table 232