manualshive.com logo in svg

NXP Semiconductors LPC822M101JDH20, User Manual, Page: 180 / 487

Share
Download
NXP Semiconductors LPC822M101JDH20 User Manual Download Page 180

UM10800

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2016. All rights reserved.

User manual

Rev. 1.2 — 5 October 2016 

180 of 487

NXP Semiconductors

UM10800

Chapter 12: LPC82x DMA controller

 

12.6.17 Channel control and status registers

The CTLSTATn register provides status flags specific to DMA channel n.

 

Table 171. Trigger setting summary

TrigBurst TrigType

TrigPol

Description

0

0

0

Hardware  DMA  trigger  is  falling  edge  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap.

0

0

1

Hardware  DMA  trigger  is  rising  edge  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap.

0

1

0

Hardware  DMA  trigger  is  low  level  sensitive.  The  BURSTPOWER  field  controls  address 
wrapping if enabled via SrcBurstWrap and/or DstBurstWrap.

0

1

1

Hardware  DMA  trigger  is  high  level  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap.

1

0

0

Hardware  DMA  trigger  is  falling  edge  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also 
determines how much data is transferred for each trigger.

1

0

1

Hardware  DMA  trigger  is  rising  edge  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also 
determines how much data is transferred for each trigger.

1

1

0

Hardware  DMA  trigger  is  low  level  sensitive.  The  BURSTPOWER  field  controls  address 
wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also determines how 
much data is transferred for each trigger.

1

1

1

Hardware  DMA  trigger  is  high  level  sensitive.  The  BURSTPOWER  field  controls 
address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also 
determines how much data is transferred for each trigger.

Table 172. Control and Status registers for channel 0 to 17 (CTLSTAT[0:17], 0x5000 8404 (CTLSTAT0) to address 

0x5000 8514 (CTLSTAT17)) bit description

Bit

Symbol

Value Description

Reset 
value

0

VALIDPENDING

Valid pending flag for this channel. This bit is set when a 1 is written to the 
corresponding bit in the related SETVALID register when CFGVALID = 1 for the 
same channel.

0

0

No effect on DMA operation.

1

Valid pending.

1

-

Reserved. Read value is undefined, only zero should be written.

NA

2

TRIG

Trigger flag. Indicates that the trigger for this channel is currently set. This bit is 
cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.

0

0

Not triggered. The trigger for this DMA channel is not set. DMA operations will 
not be carried out.

1

Triggered. The trigger for this DMA channel is set. DMA operations will be 
carried out.

31:3

-

Reserved. Read value is undefined, only zero should be written.

NA

Summary of Contents for LPC822M101JDH20

Page 1: ...manual Rev 1 2 5 October 2016 User manual Document information Info Content Keywords LPC82x LPC824M201JHI33 LPC822M101JHI33 LPC824M201JDH20 LPC822M101JDH20 LPC82x UM LPC82x user manual LPC820 Abstract...

Page 2: ...h in Section 26 5 1 1 Param0 system PLL input frequency and Param1 expected system clock Updated Section 25 6 2 IAP commands Updated Table 308 LPC82x flash configuration corrected the page numbers of...

Page 3: ...MHz with single cycle multiplier and fast single cycle I O port ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC System tick timer AHB multilayer matrix Serial Wire Debug SWD with four...

Page 4: ...ut pins and external or internal reference voltage Serial peripherals Three USART interfaces with pin functions assigned through the switch matrix and one common fractional baud rate generator Two SPI...

Page 5: ...GPIO access at address 0xA000 0000 The ARM Cortex M0 core version is r0p1 The core includes a single cycle multiplier and a system tick timer SysTick Table 1 Ordering information Type number Package N...

Page 6: ...B ARM CORTEX M0 TEST DEBUG INTERFACE FLASH 16 32 KB HIGH SPEED GPIO AHB TO APB BRIDGE CLOCK GENERATION POWER CONTROL SYSTEM FUNCTIONS RESET CLKIN clocks and controls LPC82xM aaa 014399 slave slave sla...

Page 7: ...e 2 shows the overall map of the entire address space from the user program viewpoint following reset The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals Each pe...

Page 8: ...reserved 12 bit ADC self wake up timer reserved WWDT analog comparator PMU 30 31 reserved 0 1 2 3 4 5 6 7 8 9 0x4002 C000 0x4003 0000 0x4003 4000 DMA TRIGMUX 10 input mux 11 reserved 12 reserved 13 1...

Page 9: ...onfiguration is required to use the ROM APIs 3 4 Pin description When the ISP entry pin is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up In ISP mode pin PIO0_0 is...

Page 10: ...it may take up to 3 ms before the ISP entry pin is sampled and the decision whether to continue with user code or ISP handler is made The bootloader performs the following steps see Figure 4 1 If the...

Page 11: ...0x0 0x4 0x8 0x10 0x14 0xC Device 3 Power profiles API function table IAP calls Ptr to IAP 0x1FFF 1FF1 Pointer to power profiles function table 0x18 Device 7 SPI driver routines function table Device...

Page 12: ...ry area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described in Section 25 7 2 Memory and interrupt use for ISP and IAP The interrupt vectors residing in the boot...

Page 13: ...In response the host should send the same string Synchronized CR LF The bootloader auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK C...

Page 14: ...auto baud in software 2 This step is included for backward compatibility and the response is ignored by the bootloader Fig 4 Boot process flowchart RESET INITIALIZE RECEIVE CRYSTAL FREQUENCY 2 RUN UAR...

Page 15: ...allows for low interrupt latency and efficient processing of late arriving interrupts 4 3 1 Interrupt sources Table 5 lists the interrupt sources for each peripheral function Each peripheral device m...

Page 16: ...t COMPEDGE rising falling or both edges can set the bit 12 WDT_IRQ Windowed watchdog timer interrupt WARNINT watchdog warning interrupt 13 BOD_IRQ BOD interrupts BODINTVAL BOD interrupt level 14 FLASH...

Page 17: ...dresses also called exception vectors for all exception handlers On system reset the vector table is located at address 0x0000 0000 Software can write to the VTOR register in the NVIC to relocate the...

Page 18: ...ctive state for specific peripheral functions 0 Table 11 0x304 Reserved 0 IPR0 RW 0x400 Interrupt Priority Registers 0 This register allows assigning a priority to each interrupt This register contain...

Page 19: ...escription Reset value 0 ISE_SPI0 Interrupt enable 0 1 ISE_SPI1 Interrupt enable 0 2 Reserved 3 ISE_UART0 Interrupt enable 0 4 ISE_UART1 Interrupt enable 0 5 ISE_UART2 Interrupt enable 0 6 Reserved 7...

Page 20: ...e 0 ICE_SPI0 Interrupt disable 0 1 ICE_SPI1 Interrupt disable 0 2 Reserved 3 ICE_UART0 Interrupt disable 0 4 ICE_UART1 Interrupt disable 0 5 ICE_UART2 Interrupt disable 0 6 Reserved 7 ICE_I2C1 Interru...

Page 21: ...description Bit Symbol Description Reset value 0 ISP_SPI0 Interrupt pending set 0 1 ISP_SPI1 Interrupt pending set 0 2 Reserved 3 ISP_UART0 Interrupt pending set 0 4 ISP_UART1 Interrupt pending set 0...

Page 22: ...errupt set pending register 0 register ISPR0 address 0xE000 E200 bit description continued Bit Symbol Description Reset value Table 10 Interrupt clear pending register 0 register ICPR0 address 0xE000...

Page 23: ...pt pending clear 0 28 ICP_PININT4 Interrupt pending clear 0 29 ICP_PININT5 Interrupt pending clear 0 30 ICP_PININT6 Interrupt pending clear 0 31 ICP_PININT7 Interrupt pending clear 0 Table 10 Interrup...

Page 24: ...Interrupt active 0 31 IAB_PININT7 Interrupt active 0 Table 11 Interrupt Active Bit Register 0 IABR0 address 0xE000 E300 bit description Bit Symbol Function Reset value Table 12 Interrupt Priority Reg...

Page 25: ...bits ignore writes and read as 0 23 22 IP_MRT Interrupt Priority 0 highest priority 3 lowest priority 29 24 These bits ignore writes and read as 0 31 30 IP_CMP Interrupt Priority 0 highest priority 3...

Page 26: ...riority 3 lowest priority 21 16 These bits ignore writes and read as 0 23 22 IP_I2C3 Interrupt Priority 0 highest priority 3 lowest priority 29 24 Reserved 31 30 Reserved Table 18 Interrupt Priority R...

Page 27: ...race start and stop Interrupt latency control Select a source for the NMI Calibrate system tick timer 5 3 Basic configuration Configure the SYSCON block as follows The SYSCON uses the CLKIN CLKOUT RES...

Page 28: ...ct the main clock You have the following options IRC 12 MHz internal oscillator default PLL output You must configure the PLL to use the PLL output Section 5 6 11 Main clock source select register 2 U...

Page 29: ...reset input 5 5 General description 5 5 1 Clock generation The system control block generates all clocks for the chip Only the low power oscillator used for wake up timing is controlled by the PMU Exc...

Page 30: ...6 6 Watchdog oscillator control register Section 5 6 5 System oscillator control register Fig 5 Clock generation SYSTEM PLL watchdog oscillator IRC oscillator IRC oscillator watchdog oscillator SYSTE...

Page 31: ...ss boundaries Details of the registers appear in the description of each function Reset values describe the content of the registers after the bootloader has executed All address offsets not shown in...

Page 32: ...ble 44 IOCONCLKDIV3 R W 0x140 Peripheral clock 3 to the IOCON block for programmable glitch filter 0 Table 44 IOCONCLKDIV2 R W 0x144 Peripheral clock 2 to the IOCON block for programmable glitch filte...

Page 33: ...tart logic 0 pin wake up enable register 0 Table 50 STARTERP1 R W 0x214 Start logic 1 interrupt wake up enable register 0 Table 51 PDSLEEPCFG R W 0x230 Power down states in deep sleep mode 0xFFFF Tabl...

Page 34: ...SART2 reset 1 Clear the USART2 reset 6 I2C0_RST_N I2C0 reset control 1 0 Assert the I2C0 reset 1 Clear the I2C0 reset 7 MRT_RST_N Multi rate timer MRT reset control 1 0 Assert the MRT reset 1 Clear th...

Page 35: ...be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz 14 I2C1_RST_N I2C1 reset control 1 0 Assert the I2C1 reset 1 Clear the I2C1 reset 15 I2C2_RST_N I2C2 reset control 1 0...

Page 36: ...t the analog output clock Fclkana can be divided to the 6 5 PSEL Post divider ratio P The division ratio is 2 P 0 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits Table...

Page 37: ...If accurate timing is required use the IRC or system oscillator Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing...

Page 38: ...erved User manual Rev 1 2 5 October 2016 38 of 487 NXP Semiconductors UM10800 Chapter 5 LPC82x System configuration SYSCON Table 28 Internal resonant crystal control register IRCCTRL address 0x4004 80...

Page 39: ...from LOW to HIGH for the update to take effect Table 29 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0 0...

Page 40: ...toggled from 0 to 1 for the update to take effect 5 6 12 Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSE...

Page 41: ...clock cannot be disabled Table 34 System clock divider register SYSAHBCLKDIV address 0x4004 8078 bit description Bit Symbol Description Reset value 7 0 DIV System AHB clock divider values 0 System cl...

Page 42: ...for multi rate timer 0 Disable 1 Enable 11 SPI0 Enables clock for SPI0 0 0 Disable 1 Enable 12 SPI1 Enables clock for SPI1 0 Disable 1 Enable 13 CRC Enables clock for CRC 0 0 Disable 1 Enable 14 UART0...

Page 43: ...0 Disable 1 Enable 23 I2C3 Enables clock to I2C3 0 0 Disable 1 Enable 24 ADC Enables clock to ADC 0 0 Disable 1 Enable 25 Reserved 26 MTB Enables clock to micro trace buffer control registers Turn on...

Page 44: ...a one 5 6 18 CLKOUT clock divider register This register determines the divider value for the signal on the CLKOUT pin 5 6 19 USART fractional generator divider value register All USART peripherals s...

Page 45: ...k and baud rate Section 13 7 1 Clocking and baud rates 5 6 20 USART fractional generator multiplier value register All USART peripherals share a common clock U_PCLK which can be adjusted by a fraction...

Page 46: ...shut down by setting the DIV bits to 0x0 Table 41 USART fractional generator multiplier value register UARTFRGMULT address 0x4004 80F4 bit description Bit Symbol Description Reset value 7 0 MULT Numer...

Page 47: ...is register determines the value of the SYST_CALIB register Table 44 IOCON glitch filter clock divider registers 6 to 0 IOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIV0...

Page 48: ...terminism will depend on the application The default setting for this register is 0x010 5 6 27 NMI source selection register The NMI source selection register selects a peripheral interrupt as source...

Page 49: ...VIC using interrupt slots 24 to 31 see Table 5 To use the selected pins for pin interrupts or the pattern match engine see Section 10 5 2 Pattern match engine 5 6 29 Start logic 0 pin wake up enable r...

Page 50: ...interrupt 5 wake up 0 0 Disabled 1 Enabled 6 PINT6 GPIO pin interrupt 6 wake up 0 0 Disabled 1 Enabled 7 PINT7 GPIO pin interrupt 7 wake up 0 0 Disabled 1 Enabled 31 8 Reserved Table 50 Start logic 0...

Page 51: ...main running through this register The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 253 is set See Section 17 5 3 for details 5...

Page 52: ...PD Watchdog oscillator power down control for Deep sleep and Power down mode Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog...

Page 53: ...the system oscillator Therefore add a software delay of about 500 s before using the system oscillator after power up 6 WDTOSC_PD Watchdog oscillator wake up configuration Changing this bit to powered...

Page 54: ...1 Powered down 6 WDTOSC_PD Watchdog oscillator power down Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is alw...

Page 55: ...sertion of any reset source ARM core software reset POR BOD reset External reset and Watchdog reset the following processes are initiated 1 The IRC starts up After the IRC start up time maximum of 6 s...

Page 56: ...al can be enabled for interrupt in the Interrupt Enable Register in the NVIC see Table 6 in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register...

Page 57: ...he divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz because the main clock is limited to a maximum frequency of 100 MHz 5 7 4 1 Lock det...

Page 58: ...lock is the decimal value on MSEL bits plus one as specified in Table 24 5 7 4 3 3 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way...

Page 59: ...d divider values conform to the limits specified in Table 24 Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz Table 57 shows...

Page 60: ...he internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down mode the lock output...

Page 61: ...supply voltage VDD is below 2 2 V See Table 63 If using the WKTCLKIN function disable the hysteresis for that pin in the DPDCTRL register See Table 63 6 3 1 Low power modes in the ARM Cortex M0 core E...

Page 62: ...ode Table 58 System control register SCR address 0xE000 ED10 bit description Bit Symbol Description Reset value 0 Reserved 0 1 SLEEPONEXIT Indicates sleep on exit when returning from Handler mode to T...

Page 63: ...nual Rev 1 2 5 October 2016 63 of 487 NXP Semiconductors UM10800 Chapter 6 LPC82x Reduced power modes and power management 6 5 General description Power on the LPC800 is controlled by the PMU by the S...

Page 64: ...r maximal power savings the entire system is shut down except for the general purpose registers in the PMU and the self wake up timer Only the general purpose registers in the PMU maintain their inter...

Page 65: ...DPDCTRL register in the PCON block Select low power clock for WKT clock in the WKT CTRL register Start the WKT by writing a time out value to the WKT COUNT register Interrupt from USART SPI I2C periph...

Page 66: ...l Value Description Reset value 2 0 PM Power mode 000 0x0 Default The part is in active or sleep mode 0x1 Deep sleep mode ARM WFI will enter Deep sleep mode 0x2 Power down mode ARM WFI will enter Powe...

Page 67: ...ed the self wake up timer if the wake up pin is used for other purposes and the wake up function is not available Table 62 General purpose registers 0 to 3 GPREG 0 3 address 0x4002 0004 GPREG0 to 0x40...

Page 68: ...Deep power down mode 0 0 Disabled 1 Enabled 4 WAKEUPCLKHYS External clock input for the self wake up timer WKTCLKIN hysteresis enable 0 0 Disabled Hysteresis for WAKEUP clock pin disabled 1 Enabled Hy...

Page 69: ...he following configuration choices The SYSAHBCLKCTRL register controls which memories and peripherals are running Table 35 The power to various analog blocks PLL oscillators the BOD circuit and the fl...

Page 70: ...t WFI instruction 6 7 4 3 Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs After wake up due to an interrupt...

Page 71: ...e 50 and in the NVIC BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the deep sleep interrupt wake up register 1 Table 51 The BOD interrupt must be enabled in the NVIC...

Page 72: ...OD circuit can be left running in Power down mode if required by the application 6 7 6 2 Programming Power down mode The following steps must be performed to enter Power down mode 1 The PM bits in the...

Page 73: ...pin In this mode you must pull the RESET pin HIGH externally Remark Setting bit 3 in the PCON register Table 61 prevents the part from entering Deep power down mode 6 7 7 1 Power configuration in Dee...

Page 74: ...e Table 63 2 Ensure that bit 3 in the PCON register Table 61 is cleared 3 Write 0x3 to the PM bits in the PCON register see Table 61 4 Store data to be retained in the general purpose registers Sectio...

Page 75: ...n assignment registers After the switch matrix is configured disable the clock to the switch matrix block in the SYSAHBCLKCTRL register Before activating a peripheral or enabling its interrupt use the...

Page 76: ...cription table to find the default GPIO function PIO0_n assigned to package pin x m is the pin number 4 Locate the pin assignment register for the function FUNC in the switch matrix register descripti...

Page 77: ...F 4 Clear all pending interrupts for the disconnected peripheral and ensure that the peripheral is in a defined state 5 In the pin assign register for the new pin function program the pin number 6 Dis...

Page 78: ...multiple internal inputs by programming the same pin number in more than one PINASSIGN register Example You can enable the CLKIN input in the PINENABLE0 register on pin PIO0_1 and also assign one ore...

Page 79: ...GN2 Table 69 U2_TXD O Transmitter output for USART2 PINASSIGN2 Table 69 U2_RXD I Receiver input for USART2 PINASSIGN2 Table 69 U2_RTS O Request To Send output for USART1 PINASSIGN3 Table 70 U2_CTS I C...

Page 80: ...ions PINENABLE0 Some functions require pins with special characteristics and cannot be moved to other physical pins Hence these functions are mapped to a fixed port pin Examples of fixed pin functions...

Page 81: ...U1_TXD U1_RXD U1_RTS 0xFFFF FFFF Table 68 PINASSIGN2 R W 0x008 Pin assign register 2 Assign movable functions U1_CTS U1_SCLK U2_TXD U2_RXD 0xFFFF FFFF Table 69 PINASSIGN3 R W 0x00C Pin assign registe...

Page 82: ...0 to PIO0_28 0x1C 0xFF 15 8 U0_RXD_I U0_RXD function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_28 0x1C 0xFF 23 16 U0_RTS...

Page 83: ...lue is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_28 0x1C 0xFF Table 70 Pin assign register 3 PINASSIGN3 address 0x4000 C00C bit description Bit S...

Page 84: ...pins are available PIO0_0 0 to PIO0_28 0x1C 0xFF 15 8 SPI0_SSEL3_I O SPI0_SSEL3 function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0...

Page 85: ...e value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_28 0x1C 0xFF Table 75 Pin assign register 8 PINASSIGN8 address 0x4000 C020 bit description B...

Page 86: ...are available PIO0_0 0 to PIO0_28 0x1C 0xFF 15 8 I2C3_SDA_IO I2C3_SDA function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_...

Page 87: ...P_I4 ACMP_I4 function select 1 0 ACMP_I4 enabled on pin PIO0_23 1 ACMP_I4 disabled 4 SWCLK SWCLK function select 0 0 SWCLK enabled on pin PIO0_3 1 SWCLK disabled 5 SWDIO SWDIO function select 0 0 SWDI...

Page 88: ...unction select 1 0 ADC_4 enabled on pin PIO0_22 1 ADC_4 disabled 18 ADC_5 ADC_5 function select 1 0 ADC_5 enabled on pin PIO0_21 1 ADC_5 disabled 19 ADC_6 ADC_6 function select 1 0 ADC_6 enabled on pi...

Page 89: ...pins PIO0_10 and PIO0_11 can be configured for different I2C bus speeds 8 3 Basic configuration Enable the clock to the IOCON in the SYSAHBCLKCTRL register Table 35 bit 18 Once the pins are configured...

Page 90: ...pecific pin Related links Table 65 Movable functions assign to pins PIO0_0 to PIO0_28 through switch matrix 8 4 3 Pin mode The MODE bit in the IOCON register allows enabling or disabling an on chip pu...

Page 91: ...ed all three I2C modes Standard mode Fast mode and Fast mode plus are supported A digital glitch filter can be configured for all functions Pins PIO0_10 and PIO0_11 operate as high current sink driver...

Page 92: ...pin PIO0_12 0x0000 0090 Table 85 PIO0_5 R W 0x00C I O configuration for pin PIO0_5 RESET 0x0000 0090 Table 86 PIO0_4 R W 0x010 I O configuration for pin PIO0_4 ADC_11 TRSTN WAKEUP 0x0000 0090 Table 87...

Page 93: ...0_20 R W 0x070 I O configuration for pin PIO0_20 ADC_6 0x0000 0090 Table 109 PIO0_19 R W 0x074 I O configuration for pin PIO0_19 ADC_7 0x0000 0090 Table 110 PIO0_18 R W 0x078 I O configuration for pin...

Page 94: ...6 0x058 no no yes no Table 103 PIO0_27 0x054 no no yes no Table 102 PIO0_28 0x050 no no yes no Table 101 Table 82 I O configuration registers ordered by pin name Name Address offset True open drain An...

Page 95: ...ampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 Table 83 PIO0_17 register...

Page 96: ..._DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 I...

Page 97: ...3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock Value 0x7 is reserved 0 0x0 IOCONCLKDIV0 0x1 I...

Page 98: ...ck are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select periphera...

Page 99: ...2 11 S_MODE Digital filter sample mode 0 0x0 Bypass input filter 0x1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clock...

Page 100: ...reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 S_MODE Digital filter sample mode 0 0x0...

Page 101: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drai...

Page 102: ...ndard mode I2CMODE 00 default or Standard I O functionality I2CMODE 01 if the pin function is GPIO 00 0x0 Standard mode Fast mode I2C 0x1 Standard GPIO functionality Requires external pull up for GPIO...

Page 103: ...ndard mode I2CMODE 00 default or Standard I O functionality I2CMODE 01 if the pin function is GPIO 00 0x0 Standard mode Fast mode I2C 0x1 Standard GPIO functionality Requires external pull up for GPIO...

Page 104: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dr...

Page 105: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dr...

Page 106: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dra...

Page 107: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain...

Page 108: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dra...

Page 109: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dra...

Page 110: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain...

Page 111: ...Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open dra...

Page 112: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 113: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 114: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 115: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 116: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 117: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 118: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 119: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 120: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 121: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 122: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 123: ...0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open d...

Page 124: ...The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts The GPIOs can be used as external interrupts toget...

Page 125: ...o B28 R W 0x0000 to 0x001C Byte pin registers port 0 pins PIO0_0 to PIO0_28 ext byte 8 bit Table 114 W0 to W28 R W 0x1000 to 0x1074 Word pin registers port 0 ext word 32 bit Table 115 DIR0 R W 0x2000...

Page 126: ...of the Mask register Table 115 GPIO port word pin registers W 0 28 addresses 0xA000 1000 W0 to 0xA000 1074 W28 bit description Bit Symbol Description Reset value Access 31 0 PWORD Read 0 pin PIOm_n is...

Page 127: ...Table 118 GPIO port pin register PIN0 address 0xA000 2100 bit description Bit Symbol Description Reset value Access 28 0 PORT Reads pin states or loads output bits bit 0 PIO0_0 bit 1 PIO0_1 bit 38 PIO...

Page 128: ...0xA000 2280 bit description Bit Symbol Description Reset value Access 28 0 CLRP Clear output bits bit 0 PIO0_0 bit 1 PIO0_1 bit 28 PIO0_28 0 No operation 1 Clear output bit NA WO 31 29 Reserved 0 Tab...

Page 129: ...GPIO block These output bits are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driven onto the pin 1 The pin must be selected for GPIO o...

Page 130: ...done by interrupt disabling or by using a semaphore The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them af...

Page 131: ...an be programmed to also generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin Pattern match can be used in conjunction with software to create complex state machines...

Page 132: ...rk The port pin number serves to identify the pin to the PINTSEL register Any function including GPIO can be assigned to this pin through the switch matrix 3 Enable each pin interrupt in the NVIC Once...

Page 133: ...to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts Each term in the boolean expression is implemented as one slice of the pattern match engine A sli...

Page 134: ...logic block Fig 12 Pattern match engine connections PMSCR bits SCRn n n IN0 IN7 PMSCR bits SCRn 1 IN0 IN7 DETECT LOGIC PINTSEL0 PINTSEL7 NVIC pin interrupt n endpoint configured PMCFG bit n 1 PROD_EN...

Page 135: ...vel on the selected input Figure 13 shows the details of the edge detection logic for each slice You can combine a sticky event with non sticky events to create a pin interrupt whenever a rising or fa...

Page 136: ...structed of eight bit slice elements Each bit slice is programmed to represent one component of one minterm product term within the boolean expression The interrupt request associated with the last bi...

Page 137: ...er 0 Table 129 SIENR WO 0x008 Pin interrupt level or rising edge interrupt set register NA Table 130 CIENR WO 0x00C Pin interrupt level rising edge interrupt clear register NA Table 131 IENF R W 0x010...

Page 138: ...0 the rising edge interrupt is set If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set 10 6 4 Pin interrupt level or rising edge interrupt clear register For each of the 8...

Page 139: ...ne bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the...

Page 140: ...registers regardless of whether they are interrupt enabled Table 133 Pin interrupt active level or falling edge interrupt set register SIENF address 0xA000 4014 bit description Bit Symbol Description...

Page 141: ...eneration as opposed to pin interrupts which share the same interrupt request lines and another to enable the RXEV output to the cpu This register also allows the current state of any pattern matches...

Page 142: ...pattern match feature by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros will erase all edge detect history Table 138 Pattern match interrupt control register PMCTRL ad...

Page 143: ...the pin selected in the PINTSEL6 register as the source to bit slice 0 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 0 13 11 SRC1 Selects the input source fo...

Page 144: ...the pin selected in the PINTSEL6 register as the source to bit slice 2 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 2 19 17 SRC3 Selects the input source fo...

Page 145: ...the pin selected in the PINTSEL6 register as the source to bit slice 4 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 4 25 23 SRC5 Selects the input source fo...

Page 146: ...the PINTSEL3 register as the source to bit slice 6 0x4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 6 0x5 Input 5 Selects the pin selected in the PINTSEL5 regis...

Page 147: ...t term is detected 2 The next bit slice will start a new independent product term in the boolean expression i e an OR will be inserted in the boolean expression following the element controlled by thi...

Page 148: ...leared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the...

Page 149: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 16 14 CFG2 Specifies the match contribution co...

Page 150: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 22 20 CFG4 Specifies the match contribution co...

Page 151: ...her a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 28 26 CFG6 Specifies the match contribution co...

Page 152: ...put has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge M...

Page 153: ...for bit slice 2 SRC3 010 select input 2 for bit slice 3 SRC4 011 select input 3 for bit slice 4 SRC5 110 select input 6 for bit slice 5 SRC6 101 select input 5 for bit slice 6 SRC7 111 select input 7...

Page 154: ...match on the last term Bit1 Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression Otherwise the RXEV line wil...

Page 155: ...ction IN1 SRC1 1 CFG1 0x7 PROD_ENPTS1 0x1 non sticky edge detection NVIC pin interrupt 1 and GPIO_INT_BMAT output slice 0 IN0 slice 1 IN1ev minterm IN0 IN1ev pin interrupt raised on rising edge of IN1...

Page 156: ...t multiplexer Multiplexer inputs from external pins are assigned through the switch matrix to pins 11 5 General description The inputs to the four SCTs to the DMA trigger to the eight pin interrupts a...

Page 157: ...7 SCT input multiplexing SCT SCT0_INMUX0 0 SCT0_INMUX3 3 4 SCT inputs switch matrix SCT_PIN 0 3 ADC_THCMP_IRQ ACMP0 output ARM_TXEV DEBUG_HALTED 4 switch matrix SCT_PIN 0 3 ADC_THCMP_IRQ ACMP0 output...

Page 158: ...elects from ADC SCT ACMP pin interrupts and DMA requests 0x0F Table 145 DMA_ITRIG_INMUX5 R W 0x014 Input mux register for trigger inputs 0 to 23 connected to DMA channel 0 Selects from ADC SCT ACMP pi...

Page 159: ...o 23 connected to DMA channel 0 Selects from ADC SCT ACMP pin interrupts and DMA requests 0x0F Table 145 Table 143 Register overview Input multiplexing base address 0x4002 8000 continued Name Access O...

Page 160: ...er ranging from 0 for pin function SCT_IN0 to 7 for the DEBUG_HALTED signal from the ARM CoreSight debug signal Inputs 0 to 3 are connected to external pins through the switch matrix 0x7 DMA trigger m...

Page 161: ...Rev 1 2 5 October 2016 161 of 487 NXP Semiconductors UM10800 Chapter 11 LPC82x Input multiplexing and DMA trigger multiplexing 0x6 ARM_TXEV 0x7 DEBUG_HALTED 31 4 Reserved Table 147 SCT input mux regis...

Page 162: ...The DMA interrupt is connected to slot 20 in the NVIC Each DMA channel has one DMA request line associated and can also select one of nine input triggers through the input multiplexer registers DMA_I...

Page 163: ...ls Each channel supports one DMA request line and one trigger input which is multiplexed to many possible input sources For each trigger multiplexer DMA_ITRIG_INMUXn the following sources are supporte...

Page 164: ...rs An operation on a DMA channel can be initiated by either a DMA request or a trigger event DMA requests come from peripherals and specifically indicate when a peripheral either needs input data to b...

Page 165: ...ays of using the DMA controller that have commonly used terminology in the industry Once the DMA controller is set up for operation using any specific DMA channel requires initializing the registers a...

Page 166: ...transfers A ping pong transfer uses two buffers alternately At any one time one buffer is being loaded or unloaded by DMA operations The other buffer has the opposite operation being handled by softwa...

Page 167: ...52 The difference would be that descriptor B would not link back to descriptor A but would continue on to another different descriptor This could continue as long as desired and can be ended anywhere...

Page 168: ...o auto trigger itself setup channels x and y for channel chaining as described above In addition to that A ping pong configuration for both channel x and y is recommended so that data currently moved...

Page 169: ...Transfer configuration register for DMA channel 0 Table 173 Channel1 registers CFG1 R W 0x410 Configuration register for DMA channel 1 Table 170 CTLSTAT1 RO 0x414 Control and status register for DMA...

Page 170: ...G11 R W 0x4B0 Configuration register for DMA channel 11 Table 170 CTLSTAT11 RO 0x4B4 Control and status register for DMA channel 11 Table 172 XFERCFG11 R W 0x4B8 Transfer configuration register for DM...

Page 171: ...R W 0x508 Transfer configuration register for DMA channel 16 Table 173 Channel17 registers CFG17 R W 0x510 Configuration register for DMA channel 17 Table 170 CTLSTAT17 RO 0x514 Control and status re...

Page 172: ...e DMA controller is disabled This clears any triggers that were asserted at the point when disabled but does not prevent re triggering when the DMA controller is re enabled 1 Enabled The DMA controlle...

Page 173: ...bit enabling the related DMA channel Writing a 0 to any bit has no effect Enables are cleared by writing to ENABLECLR0 Table 157 Channel descriptor map Descriptor Table offset Channel descriptor for...

Page 174: ...r The BUSY0 register indicates which DMA channels is busy at the point when the read occurs This registers is read only A DMA channel is considered busy when there is any operation related to that cha...

Page 175: ...0 that corresponds to an implemented DMA channel sets the bit enabling the interrupt for the related DMA channel Writing a 0 to any bit has no effect Interrupt enables are cleared by writing to INTENC...

Page 176: ...this register The error status is reported in the ERRINT0 status register 12 6 13 Set Valid register The SETVALID0 register allows setting the Valid bit in the CTRLSTAT register for one or more DMA c...

Page 177: ...clearing the corresponding Enable bit by writing a 1 to the proper bit ENABLECLR Then wait until the channel is no longer busy by checking the corresponding bit in BUSY Finally write a 1 to the proper...

Page 178: ...nel 0 0 Active low falling edge Hardware trigger is active low or falling edge triggered based on TRIGTYPE 1 Active high rising edge Hardware trigger is active high or rising edge triggered based on T...

Page 179: ...abled the source data address for the DMA is wrapped meaning that the source address range for each burst will be the same As an example this could be used to read several sequential registers from a...

Page 180: ...BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and or DstBurstWrap and also determines how much data is transferred for each trigger 1 1 0 Hardware DMA trigger is low level se...

Page 181: ...ked transfers 0 0 Disabled Do not reload the channels control structure when the current descriptor is exhausted 1 Enabled Reload the channels control structure when the current descriptor is exhauste...

Page 182: ...each transfer 0x3 4 x width The source address is incremented by 4 times the amount specified by Width for each transfer 15 14 DSTINC Determines whether the destination address is incremented for each...

Page 183: ...Hardware triggering requires setup of the HWTRIGEN TRIGPOL TRIGTYPE and TRIGBURST fields in the CFG register for the related channel When a channel is initially set up the SWTRIG bit in the XFERCFG re...

Page 184: ...egister Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator with autobaud function A fractional rate divider is sha...

Page 185: ...USART clock divider register UARTCLKDIV address 0x4004 8094 bit description 2 If a fractional value is needed to obtain a particular baud rate program the fractional divider The fractional divider val...

Page 186: ...he USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM core that is in Deep sleep or Power down mode As long as the USART receives a cloc...

Page 187: ...nterrupt and are also enabled in the INTENSET register Typical wake up events are A start bit has been received The RXDAT buffer has received a byte Data is ready to be transmitted in the TXDAT buffer...

Page 188: ...feature is active when enabled by the CTSEn bit in CFG register and when configured to appear on a device pin When de asserted high by the external device the USART will complete transmitting any char...

Page 189: ...is transmitted and received using the baud rate clock without division Status information from the transmitter and receiver is saved and provided via the Stat register Many of the status flags are ab...

Page 190: ...upt Enable read and Set register Contains an individual interrupt enable bit for each potential USART interrupt A complete value may be read from this register Writing a 1 to any implemented bit posit...

Page 191: ...t other control bits remain unchanged For instance when re enabled the USART will immediately generate a TXRDY interrupt if enabled in the INTENSET register or a DMA transfer request because the trans...

Page 192: ...Master select 0 0 Slave When synchronous mode is enabled the USART is a slave 1 Master When synchronous mode is enabled the USART is a master 15 LOOP Selects data loopback mode 0 0 Normal operation 1...

Page 193: ...rol an RS 485 transceiver 21 OEPOL Output Enable Polarity 0 0 Low If selected by OESEL the output enable is active low 1 High If selected by OESEL the output enable is active high 22 RXPOL Receive dat...

Page 194: ...eats the incoming data normally generating a received data interrupt Software can then check the data to see if this is an address that should be handled If it is the ADDRDET bit is cleared by softwar...

Page 195: ...nly zero should be written NA Table 177 USART Control register CTL address 0x4006 4004 USART0 0x4006 8004 USART1 0x4006 C004 USART2 bit description Bit Symbol Value Description Reset value Table 178 U...

Page 196: ...on occurs because the stop bit s for the character would be missing RXBRK is cleared when the Un_RXD pin goes high 0 RO 11 DELTARXBRK This bit is set when a change in the state of receiver break detec...

Page 197: ...defined only zero should be written NA 5 DELTACTSEN When 1 enables an interrupt when there is a change in the state of the CTS input 0 6 TXDISEN When 1 enables an interrupt when the transmitter is ful...

Page 198: ...rs the corresponding bit in the INTENSET register 0 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register 0 6...

Page 199: ...r of bits that are relevant depends on the USART configuration settings 0 31 9 Reserved the value read from a reserved bit is not defined NA Table 182 USART Receiver Data with Status register RXDATSTA...

Page 200: ...RT is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire registers 3 Write the new BRGVAL 4 Write to the CFG register to set th...

Page 201: ...ue is undefined only zero should be written NA 2 TXRDY Transmitter Ready flag 1 3 TXIDLE Transmitter idle status 1 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTS This bit...

Page 202: ...address for hardware address matching in address detect mode with automatic address matching enabled 13 7 Functional description 13 7 1 Clocking and baud rates In order to use the USART clocking detai...

Page 203: ...d by the FRG cannot be perfectly symmetrical so the FRG distributes the output clocks as evenly as is practical Since the USART normally uses 16x overclocking the jitter in the fractional rate clock i...

Page 204: ...vice it indicates to an external device the ability of the receiver to receive more data If connected to a pin and if enabled to do so the CTS input can allow an external device to throttle the USART...

Page 205: ...ister in Section 13 6 2 Automatic data direction control with the RTS pin can be set up using the OESEL OEPOL and OETA bits in the CFG register Section 13 6 1 Data direction control can also be implem...

Page 206: ...ts reserved User manual Rev 1 2 5 October 2016 206 of 487 NXP Semiconductors UM10800 Chapter 13 LPC82x USART0 1 2 oversample clocks before actual data sampling is done making the sampling more robust...

Page 207: ...polarity and flexible usage Supports DMA transfers SPIn transmit and receive functions can operated with the system DMA controller Remark Texas Instruments SSI and National Microwire modes are not su...

Page 208: ...leep mode Configure the SPI in either master or slave mode See Table 190 Enable the SPI interrupt in the NVIC Any SPI interrupt wakes up the part from sleep mode Enable the SPI interrupt in the INTENS...

Page 209: ...to the master When the SPI is a master serial data is input from this signal When the SPI is a slave serial data is output to this signal MISO is driven when the SPI block is enabled the Master bit i...

Page 210: ...upt enables Fig 24 SPI block diagram MISO MOSI SSEL 3 0 SCK Pad interface Rx Shift Register State Machine Tx Shift Register State Machine SPIn_TXDAT SPIn_RXDAT General controls format configurations 1...

Page 211: ...in INTENSET to be cleared NA Table 194 RXDAT R 0x014 SPI Receive Data NA Table 195 TXDATCTL R W 0x018 SPI Transmit Data with Control 0 Table 196 TXDAT R W 0x01C SPI Transmit Data 0 Table 197 TXCTL R W...

Page 212: ...e in the SSEL0 fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL0 is not inverted relative to the pins 1 High The SSEL0 pin is active high The value in the SSEL0 fields of the RXDAT TXD...

Page 213: ...AY Controls the amount of time between the end of a data transfer and SSEL deassertion 0x0 No additional time is inserted 0x1 1 SPI clock time is inserted 0x2 2 SPI clock times are inserted 0xF 15 SPI...

Page 214: ...XDAT or TXDATCTL until the data is moved to the transmit shift register 1 RO 2 RXOV Receiver Overrun interrupt flag This flag applies only to slave mode Master 0 This flag is set when the beginning of...

Page 215: ...process of sending data 1 RO 31 9 Reserved Read value is undefined only zero should be written NA NA Table 192 SPI Status register STAT addresses 0x4005 8008 SPI0 0x4005 C008 SPI1 bit description Bit...

Page 216: ...Slave Select is deasserted 0 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted 1 An interrupt will be generated when all asserted Slave Selects transition to d...

Page 217: ...pin for both master and slave operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG undefined 18 RXSSEL2_N...

Page 218: ...mply provide two ways to access them For details on the slave select process see Section 14 7 4 For details on using multiple consecutive data transmits for transfer lengths larger than 16 bit see Sec...

Page 219: ...e lengths greater than 16 bits 0 0 Data not EOF This piece of data transmitted is not treated as the end of a frame 1 Data EOF This piece of data is treated as the end of a frame causing the FRAME_DEL...

Page 220: ...ister determines the clock used by the SPI in master mode For details on clocking see Section 14 7 3 Clocking and data rates Table 197 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPI0 0x...

Page 221: ...n Reset Value 15 0 DIVVAL Rate divider value Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode DIVVAL is 1 encoded such that the value 0 results in PCLK 1 the...

Page 222: ...CPOL CPHA SPI Mode Description SCKrest state SCK data change edge SCK data sample edge 0 0 0 The SPI captures serial data on the first clock transition of the transfer when the clock changes away from...

Page 223: ...minimum duration of SSEL in the de asserted state between transfers 14 7 2 1 Pre_delay and Post_delay Pre_delay and Post_delay are illustrated by the examples in Figure 26 The Pre_delay value control...

Page 224: ...y the examples in Figure 27 Note that frame boundaries occur only where specified This is because frame lengths can be any size involving multiple data writes See Section 14 7 6 for more information F...

Page 225: ...ransfers because the EOT bit 1 When Transfer_delay 0 SSEL may be de asserted for a minimum of one SPI clock time Transfer_delay is illustrated by the examples in Figure 28 Fig 28 Transfer_delay Transf...

Page 226: ...s the selected PCLK or at lower integer divide rates The SPI rate will be PCLK_SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used 14 7 4 Slave select...

Page 227: ...er data widths depend somewhat on other SPI configuration options For instance if it is intended for Slave Selects to be de asserted between frames then this must be suppressed when a larger frame is...

Page 228: ...t_delay 0 2 clock stall Mode 2 CPOL 1 SCK Mode 0 CPOL 0 SCK MISO MOSI Second data frame Receiver stall CPHA 1 Frame_delay 0 Pre_delay 0 Post_delay 0 2 clock stall MISO MOSI Mode 1 CPOL 0 SCK Mode 3 CP...

Page 229: ...I2C slave addresses supported in hardware One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses 10 bit addressing suppor...

Page 230: ...description and Table 91 PIO0_10 register PIO0_10 address 0x4004 4020 bit description The transmission of the address and data bits is controlled by the state of the MSTPENDING status bit Whenever th...

Page 231: ...set MSTPENDING 1 by polling the STAT register 7 Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 213 15 3 1 2 Master read from slave Configure the I2C as...

Page 232: ...data The received data or the data to be sent to the master are available in the SLVDAT register After sending and receiving data continue to the next step of the transmission protocol by writing to...

Page 233: ...as the I2C clock I2C_PCLK remains active in sleep mode the I2C can wake up the part independently of whether the I2C block is configured in master or slave mode In Deep sleep or Power down mode the I2...

Page 234: ...e 91 PIO0_10 register PIO0_10 address 0x4004 4020 bit description Pins for the I2C1 2 3 interfaces are movable functions and can be assigned to any pin However except for PIO0_10 and PIO0_11 the pins...

Page 235: ...0x4007 4008 I2C3 bit description Table 209 Interrupt Enable Clear register INTENCLR address 0x4005 000C I2C0 0x4005 400C I2C1 0x4007 000C I2C2 0x4007 400C I2C3 bit description Table 210 Time out value...

Page 236: ...4005 4040 I2C1 0x4007 0040 I2C2 0x4007 4040 I2C3 bit description Table 218 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADR0 to 0x4005 0054 SLVADR3 I2C0 0x4005 4048 SLVADR0 to 0x4005 4054...

Page 237: ...le 212 MSTCTL R W 0x20 Master control register 0 Table 213 MSTTIME R W 0x24 Master timing configuration 0x77 Table 214 MSTDAT R W 0x28 Combined Master receiver and transmitter data register NA Table 2...

Page 238: ...abled Both types of time out flags will be generated and will cause interrupts if they are enabled Typically only one time out will be used in a system 4 MONCLKSTR Monitor function Clock Stretching 0...

Page 239: ...In progress Communication is in progress and the Master function is busy and cannot currently accept a command 1 Pending The Master function needs software service or is in the idle state If the maste...

Page 240: ...only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register 0 RO 0 In progress The Slave function does not currently need service 1 Pending The Slave function...

Page 241: ...will cause an interrupt when set if enabled via INTENSET This flag can be cleared by writing a 1 to this bit 0 W1 0 Not deselected The Slave function has not become deselected This does not mean that...

Page 242: ...t The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register 25 SCLTIMEOUT SCL Time out Interrupt flag Indicates when SCL has remained low longer than the time...

Page 243: ...3 regarding 10 bit addressing No 1 SLVST_RX Received data is available Slave Receiver mode Read data reply with an ACK or a NACK Yes 2 SLVST_TX Data can be transmitted Slave Transmitter mode Send data...

Page 244: ...eSel interrupt is enabled 16 MONRDYEN Monitor data Ready interrupt Enable 0 0 The MonRdy interrupt is disabled 1 The MonRdy interrupt is enabled 17 MONOVEN Monitor Overrun interrupt Enable 0 0 The Mon...

Page 245: ...ymbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented 0 3 1 Reserved Read value is und...

Page 246: ...10 I2C1 0x4007 0010 I2C2 0x4007 4010 I2C3 bit description Bit Symbol Description Reset value 3 0 TOMIN Time out time value bottom four bits These are hard wired to 0xF This gives a minimum time out of...

Page 247: ...ew data following a Start or Stop may cause undesirable side effects Table 212 I2C Interrupt Status register INTSTAT address 0x4005 0018 I2C0 0x4005 4018 I2C1 0x4007 0018 I2C2 0x4007 4018 I2C3 bit des...

Page 248: ...ymbol Value Description Reset value 0 MSTCONTINUE Master Continue This bit is write only 0 0 No effect 1 Continue Informs the Master function to continue to the next operation This must done after wri...

Page 249: ...d lengthen this time This corresponds to the parameter tLOW in the I2C bus specification I2C bus specification parameters tBUF and tSU STA have the same values and are also controlled by MSTSCLLOW 0 0...

Page 250: ...ock pre divider 0x2 4 clocks Minimum SCL high time is 4 clock of the I2C clock pre divider 0x3 5 clocks Minimum SCL high time is 5 clock of the I2C clock pre divider 0x4 6 clocks Minimum SCL high time...

Page 251: ...t Symbol Value Description Reset Value 0 SLVCONTINUE Slave Continue 0 0 No effect 1 Continue Informs the Slave function to continue to the next operation This must done after writing transmit data rea...

Page 252: ...rs do not include the address qualifier feature For handling of the general call address one of the 4 address registers can be programmed to respond to address 0 15 6 14 Slave address Qualifier 0 regi...

Page 253: ...tion from the I2C bus Table 219 Slave address Qualifier 0 register SLVQUAL0 address 0x4005 0058 I2C0 0x4005 4058 I2C1 0x4007 0058 I2C2 0x4007 4058 I2C3 bit description Bit Symbol Value Description Res...

Page 254: ...time in I2C function clocks CLKDIV 1 MSTSCLHIGH 2 SCL low time in I2C function clocks CLKDIV 1 MSTSCLLOW 2 Nominal SCL rate I2C function clock rate SCL high time SCL low time 8 MONSTART Monitor Recei...

Page 255: ...addressing Ten bit addressing is accomplished by the I2C master sending a second address byte to extend a particular range of standard 7 bit addresses In the case of the master writing to the slave th...

Page 256: ...vice will wake up when the I2C Slave function recognizes an address Monitor mode can similarly wake up the device from a reduced power mode when information becomes available 15 7 5 lnterrupt handling...

Page 257: ...following events interrupt stop limit halt the timer or change counting direction toggle outputs change the state Counter value can be loaded into capture register triggered by a match or input outpu...

Page 258: ...Enable the clock to the SCTimer PWM SCT in the SYSAHBCLKCTRL register Table 35 to enable the register interface and the peripheral clock Clear the SCT peripheral reset using the PRESETCTRL register Ta...

Page 259: ...0x4002 C02C SCT0_INMUX3 bit description to configure the SCTimer PWM input multiplexers Fig 33 SCT connections SCT SCT0_INMUX0 0 SCT0_INMUX3 3 SCT output 3 6 4 SCT outputs 0 to 5 SCT inputs SCT_PIN 0...

Page 260: ...ware with any desired level of complexity to accomplish complex waveform and timing tasks In a simple system such as a classical timer counter with capture and match capabilities all events that could...

Page 261: ...scription The register addresses of the State Configurable Timer are shown in Table 222 For most of the SCT registers the register function depends on the setting of certain other register bits Fig 34...

Page 262: ...t 0x0004 0004 Table 224 LIMIT R W 0x008 SCT limit event select register 0x0000 0000 Table 225 LIMIT_L R W 0x008 SCT limit event select register low counter 16 bit 0x0000 0000 Table 225 LIMIT_H R W 0x0...

Page 263: ...register of match channels 0 to 7 high counter 16 bit REGMOD0_H to REGMODE7_H 0 0x0000 0000 Table 241 CAP0 to CAP7 R W 0x100 to 0x11C SCT capture register of capture channel 0 to 7 REGMOD0 to REGMODE7...

Page 264: ...E R W 0x328 SCT event state register 5 0x0000 0000 Table 246 EV5_CTRL R W 0x32C SCT event control register 5 0x0000 0000 Table 247 EV6_STATE R W 0x330 SCT event state register 6 0x0000 0000 Table 246...

Page 265: ...5 0 _CLR SET CLRm yes no select event m to capture the counter value in CAPn CAPCTRL 7 0 CAPCTRL CAPCONm yes no select event m to limit the counter LIMIT LIMMSKm event m event m event m event m yes no...

Page 266: ...with a match reload register which automatically reloads the match register at the beginning of each counter cycle This register group includes the following registers One REGMODE register per match c...

Page 267: ...e dual counter mode the events can be selected independently for each output 16 6 1 6 Event select registers for capturing a counter value This group contains registers that select events which captur...

Page 268: ...hronized to the system clock The minimum pulse width on the clock input is 1 bus clock one system clock period This mode is the low power sampled clock mode 0x3 Asynchronous Mode The entire SCT module...

Page 269: ...ut 0 bit 10 input 1 bit 12 input 3 all other bits are reserved A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock before it is used to create an event If an...

Page 270: ...always reads as 0 0 4 BIDIR_L L or unified counter direction select 0 0 Up The counter counts up to a limit condition then is cleared to zero 1 Up down The counter counts up to a limit then counts dow...

Page 271: ...le purpose of creating a limit The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable disable this feature see Table 223 If UNIFY 1 in the CONFIG register only the _L bits are used If...

Page 272: ...n any of the events selected in this register occur counting is suspended that is the counter stops running and remains at its current value Event generation remains enabled and any event selected in...

Page 273: ...an be read or written individually or in a single 32 bit read or write operation 16 6 8 SCT counter register If UNIFY 1 in the CONFIG register the counter is a unified 32 bit register and both the _L...

Page 274: ...can be made to occur only in certain states Events in turn can perform the following actions set and clear outputs limit stop and start the counter cause interrupts and DMA requests modify the state...

Page 275: ...is triple synchronized to the SCT clock resulting in a stable signal that is delayed by three SCT clock cycles If the INSYNC bit is not set the SIN bit value is identical to the AIN bit value 16 6 11...

Page 276: ...gister to allow software to control the output state directly or read its current state While the counter is running outputs are set cleared or toggled only by events However using this register softw...

Page 277: ...Do not program this value 0 0x0 Set and clear do not depend on the direction of any counter 0x1 Set and clear are reversed when counter L or the unified counter is counting down 0x2 Set and clear are...

Page 278: ...ut or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register 0x2 Clear output or set based on the SETCLR1 field 0x3 Toggle output 5 4 O2RES Effect of simultaneous set and clear on output 2 0 0...

Page 279: ...L0 A 1 in this bit triggers DMA request 0 when it loads the Match_L Unified registers from the Reload_L Unified registers 31 DRQ0 This read only bit indicates the state of DMA Request 0 Note that if t...

Page 280: ...on Reset value 7 0 FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit event 0 bit 0 event 1 bit 1 event 7 bit 7 0 31 8 Reserved Table 240 SCT conflict interrupt...

Page 281: ...cond cycle 16 6 21 SCT capture registers 0 to 7 REGMODEn bit 1 These registers allow software to record the counter values upon occurrence of the events selected by the corresponding Capture Control r...

Page 282: ...egister that can enable or disable the event for each available state Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter s...

Page 283: ...n bi directional mode events can also be enabled based on the direction of count When the UNIFY bit is 0 each event is associated with a particular counter by the HEVENT bit in its event control regis...

Page 284: ...the state selected by HEVENT when this event is the highest numbered event occurring for that state 0 STATEV value is added into STATE the carry out is ignored 1 STATEV value is loaded into STATE 19...

Page 285: ...clear or set the output depending on the setting of the SETCLRn field in the OUTPUTDIRCTRL register To define the actual event that clears the output a match an I O pin toggle etc see the EVn_CTRL re...

Page 286: ...Match logic 16 7 2 Capture logic 16 7 3 Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values are comb...

Page 287: ...user defined event triggers a state change The state change is triggered through each event s EV_CTRL register in one of the following ways The event can increment the current state number by a new v...

Page 288: ...earing the prescaler When enabled by a non zero PRE field in the Control register the prescaler acts as a clock divider for the counter like a fractional part of the counter value The prescaler is cle...

Page 289: ...when its counter HALT bit is 0 In general a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled Table 250 shows when the...

Page 290: ...ycles of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and or interrupts Once configured the SCT can run con...

Page 291: ...tputs one register per output For each SCT output select which events set or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each ev...

Page 292: ...irectional mode the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register 16 7 11 Run the SCT 1 Configure th...

Page 293: ...the STATELD and STATEV fields in the EVCTRL registers for each event Write 0x1 to the EVn_STATE register of each event Writing 0x1 enables the event In effect the event is allowed to occur in a singl...

Page 294: ...ional counter BIDIR_L 0 Clock base CONFIG Uses default values for clock configuration Match Capture registers REGMODE Configure one match register for each match event by setting REGMODE_L bits 0 1 2...

Page 295: ...ses match register 0 to qualify the event Define how event 5 changes the state EV5_CTRL Set STATEV bits to 0 and the STATED bit to 1 Event 5 changes the state to state 0 Define by which events output...

Page 296: ...g operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can optionally be pro...

Page 297: ...Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF cause...

Page 298: ...t shown in the block diagram 17 5 2 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from t...

Page 299: ...October 2016 299 of 487 NXP Semiconductors UM10800 Chapter 17 LPC82x Windowed Watchdog Timer WWDT Remark Because of the synchronization step software must add a delay of three WDCLK clock cycles betwe...

Page 300: ...source is locked and can not be disabled either by software or by hardware when Sleep Deep sleep or Power down modes are entered Therefore the user must ensure that the watchdog oscillator for each po...

Page 301: ...8 Watchdog feed sequence register Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC NA Table 256 TV RO 0x00C Watchdog timer value register This...

Page 302: ...running in Sleep Deep sleep modes and Power down modes If a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up...

Page 303: ...Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practice to disab...

Page 304: ...counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event 17 6 6 Watchdog Timer Window register...

Page 305: ...31 24 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Fig 45 Early watchdog feed with windowed mode enabled 125A 1258 1259 1257 WDCL...

Page 306: ...bit 9 Table 35 to enable the clock to the register interface Clear the WKT reset using the PRESETCTRL register Table 23 The WKT interrupt is connected to interrupt 15 in the NVIC See Table 5 Enable t...

Page 307: ...equence When the counter is being used as a wake up timer this write can occur just prior to entering a reduced power mode When a starting count value is loaded the self wake up timer automatically tu...

Page 308: ...ode is entered An external clock on the WKTCLKIN pin can be used to time the self wake up timer in all low power modes including deep power down 18 6 Register description 18 6 1 Control register The W...

Page 309: ...quest which can wake up the part from any reduced power mode including Deep power down if the clock source is the low power oscillator Writing a 1 clears this status bit 2 CLEARCTR Clears the self wak...

Page 310: ...Table 35 to enable the clock to the register interface Clear the MRT reset using the PRESETCTRL register Table 23 The global MRT interrupt is connected to interrupt 10 in the NVIC 19 4 Pin description...

Page 311: ...and the timer starts to count down again While the timer is running in repeat interrupt mode you can perform the following actions Change the interval value on the next timer cycle by writing a new va...

Page 312: ...AD bit to 1 The timer immediately stops counting and moves to the idle state No interrupt is generated when the INTVALn register is updated 19 5 3 One shot bus stall mode The one shot bus stall mode s...

Page 313: ...gister 0 Table 264 TIMER1 R W 0x14 MRT1 Timer register This register reads the value of the down counter 0x7FFF FFFF Table 265 CTRL1 R W 0x18 MRT1 Control register This register controls the MRT1 mode...

Page 314: ...he following If LOAD 1 the timer stops immediately If LOAD 0 the timer stops at the end of the time interval 0 31 LOAD Determines how the timer interval value IVALUE 1 is loaded into the TIMERn regist...

Page 315: ...e 266 Control register CTRL 0 3 address 0x4000 4008 CTRL0 to 0x4000 4038 CTRL3 bit description Bit Symbol Value Description Reset value 0 INTEN Enable the TIMERn interrupt 0 0 Disable 1 Enable 2 1 MOD...

Page 316: ...egister is also set to 1 the interrupt for timer channel 0 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 GFLAG1 Monitors the interrupt flag of TIMER1 0 0 N...

Page 317: ...k is fixed to half of the system clock frequency 2 Enable the clock source for the SysTick timer in the SYST_CSR register Table 271 3 The calibration value of the SysTick timer is contained in the SYS...

Page 318: ...and status register can be used to determine if an action completed within a set duration as part of a dynamic clock management control loop Refer to Ref 6 for details 20 6 Register description The S...

Page 319: ...ed When enabled the interrupt is generated when the System Tick counter counts down to 0 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock CPU clock is selected When 0 the syste...

Page 320: ...ST_CALIB register and may be changed by software 20 7 1 Example timer calculation To use the system tick timer do the following 1 Program the SYST_RVR register with the reload value RELOAD to obtain t...

Page 321: ...ADC as follows Use the PDRUNCFG register to power the ADC See Table 54 Once the ADC is powered by the PDRUNCFG register bit the low power mode bit in the ADC CTRL register can be used to turn off the...

Page 322: ...R TRIGPOL and SEQ_ENA bits on subsequent writes to the START bit See also Section 21 7 2 1 Avoiding spurious hardware triggers The ADC converts an analog input signal VIN on the ADC_ 11 0 The VREFP an...

Page 323: ...ting 0x1 to the TRIGGER bits in the SEQA_CTRL register 5 Assign the ADC_PINTRIG0 function to pin PIO0_15 through the switch matrix register PINASSIGN10 See Table 278 6 To generate one interrupt at the...

Page 324: ...requires approximately 290 s to complete While calibration is in progress normal ADC conversions cannot be launched and the ADC Control Register must not be written to The calibration procedure does...

Page 325: ...and reference voltage pins Function Description VREFP Positive voltage reference The VREFP voltage level must be between 2 4 V and VDDA For best performance select VREFP VDDA and VREFN VSSA VREFN Neg...

Page 326: ...converting a sample whenever a trigger signal arrives until the sequence is disabled The ADC controller uses the system clock as a bus clock The ADC clock is derived from the system clock A programmab...

Page 327: ...ster This register contains the result of the most recent conversion completed on channel 2 NA Table 285 DAT3 RO 0x02C A D Channel 3 Data Register This register contains the result of the most recent...

Page 328: ...o be used for each channel 0x0 Table 290 INTEN R W 0x064 A D Interrupt Enable Register This register contains enable bits that enable the sequence A sequence B threshold compare and data overrun inter...

Page 329: ...g circuitry is enabled After the required start up time the requested conversion will be launched Once the conversion completes the analog circuitry will again be powered down provided no further conv...

Page 330: ...t 31 is low It is safe to change this field and set bit 31 in the same write 0 0 Negative edge A negative edge launches the conversion sequence on the selected trigger input 1 Positive edge A positive...

Page 331: ...quence and launch a B sequence in it s place The conversion currently in progress will be terminated The A sequence that was interrupted will automatically resume after the B sequence completes The ch...

Page 332: ...versions are triggered by software only spurious hardware triggers must be prevented See Section 21 3 1 Perform a single ADC conversion using a software trigger Remark Set the BURST and SEQU_ENA bits...

Page 333: ...ame write 0x0 17 15 Reserved 18 TRIGPOL Select the polarity of the selected input trigger for this conversion sequence Remark In order to avoid generating a spurious trigger it is recommended writing...

Page 334: ...g with the first enabled channel Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence depending on the state of the MODE bit 0 29 Reserved...

Page 335: ...fficult for the DMA engine to address them For interrupt driven code it will more likely be advantageous to wait for an entire sequence to complete and then retrieve the results from the individual ch...

Page 336: ...was above below or within the range established by the designated threshold comparison registers THRn_LOW and THRn_HIGH 19 18 THCMPCROSS Indicates whether the result of the last conversion performed...

Page 337: ...hold register THRn_LOW but less than or equal to the value programmed into the designated HIGH threshold register THRn_HIGH 0x1 Below Range The last completed conversion on was less than the value pro...

Page 338: ...s will impact interrupt and overrun flag generation The information presented in the DAT registers always pertains to the most recent conversion completed on that channel regardless of what sequence r...

Page 339: ...programmed into the designated HIGH threshold register THRn_HIGH 0x1 Below Range The last completed conversion on was less than the value programmed into the designated LOW threshold register THRn_LOW...

Page 340: ...ular register relates to i e this field will contain 0b0000 for the DAT0 register 0b0001 for the DAT1 register etc NA 30 OVERRUN This bit will be set to a 1 if a new conversion on this channel complet...

Page 341: ...user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 4 THRLOW Low threshold value against which A D results will be compared 0x000 31 16 Reserv...

Page 342: ...rs 1 CH1_THRSEL Threshold select by channel 0 0 Threshold 0 Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers 1 Threshold 1 Channel 1 re...

Page 343: ...s will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 8 CH8_THRSEL Threshold select by channel 0 0 Threshold 0 Channel 8 results will be compared against th...

Page 344: ...led The sequence A interrupt DMA trigger is disabled 1 Enabled The sequence A interrupt DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as pa...

Page 345: ...2 Crossing threshold 0x3 Reserved 14 13 ADCMPINTEN5 Threshold comparison interrupt enable 00 0x0 Disabled 0x1 Outside threshold 0x2 Crossing threshold 0x3 Reserved 16 15 ADCMPINTEN6 Threshold comparis...

Page 346: ...software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 291 A D Interrupt Enable register INTEN address 0x4001 C064 bit description Bit Symbol Value...

Page 347: ...A D channel 0 0 13 OVERRUN1 Mirrors the OVERRRUN status flag from the result register for A D channel 1 0 14 OVERRUN2 Mirrors the OVERRRUN status flag from the result register for A D channel 2 0 15 O...

Page 348: ...n entire B sequence In this case it must be cleared by writing a 1 to this SEQB_INT bit This interrupt must be enabled in the INTEN register 0 30 THCMP_INT Threshold Comparison Interrupt DMA flag This...

Page 349: ...alternate conversion sequence is already in progress except in the case of a B trigger interrupting an A sequence if the A sequence is set to LOWPRIO If any of these conditions is true the new trigge...

Page 350: ...register is set to 1 and a software or hardware trigger for the B sequence occurs then the burst will be immediately interrupted and a B sequence will be initiated The interrupted A sequence will resu...

Page 351: ...registers are cleared when data related to that channel is read from either of the global data registers as well as when the individual data registers themselves are read 21 7 5 Optional operating mod...

Page 352: ...2 5 October 2016 352 of 487 NXP Semiconductors UM10800 Chapter 21 12 bit Analog to Digital Converter ADC 21 7 7 Hardware Trigger Source Selection Each ADC has a selection of several on chip and off c...

Page 353: ...re the analog comparator using the following registers In the SYSAHBCLKCTRL register set bit 19 Table 35 to enable the clock to the register interface You can enable or disable the power to the analog...

Page 354: ...he analog comparator can compare voltage levels on external pins and internal voltages The comparator has seven inputs multiplexed separately to its positive and negative inputs The multiplexers are c...

Page 355: ...is changed and when either or both voltage sources are changed Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result 22 5 3...

Page 356: ...ee Section 22 3 1 Connect the comparator output to the SCT 22 6 Register description 22 6 1 Comparator control register This register enables the comparator configures the interrupts and controls the...

Page 357: ...0x3 ACMP_I3 0x4 ACMP_I4 0x5 Band gap Internal reference voltage 0x6 ADC_0 ADC channel 0 input 0x7 Reserved 19 14 Reserved Write as 0 0 20 EDGECLR Interrupt clear bit To clear the COMPEDGE bit and thu...

Page 358: ...og comparator Table 297 Voltage ladder register LAD address 0x4002 4004 bit description Bit Symbol Value Description Reset value 0 LADEN Voltage ladder enable 0 5 1 LADSEL Voltage ladder value The ref...

Page 359: ...omplement programmable setting for input data and CRC sum Programmable seed number setting Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle ope...

Page 360: ...hts reserved User manual Rev 1 2 5 October 2016 360 of 487 NXP Semiconductors UM10800 Chapter 23 LPC82x CRC engine Fig 55 CRC block diagram CCIT T POLY CRC 16 POLY CRC 32 POLY CRC REG BIT REVERSE 1 s...

Page 361: ...le 301 WR_DATA WO 0x008 CRC data register Table 302 Table 299 CRC mode register MODE address 0x5000 0000 bit description Bit Symbol Description Reset value 1 0 CRC_POLY CRC polynom 1X CRC 32 polynomia...

Page 362: ...C sum NO CRC_MODE 0x0000 0000 CRC_SEED 0x0000 FFFF 23 7 2 CRC 16 set up Polynomial x16 x15 x2 1 Seed Value 0x0000 Bit order reverse for data input YES 1 s complement for data input NO Bit order revers...

Page 363: ...er 2016 363 of 487 NXP Semiconductors UM10800 Chapter 23 LPC82x CRC engine 23 7 3 CRC 32 set up Polynomial x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 x5 x4 x2 x 1 Seed Value 0xFFFF FFFF Bit order reverse f...

Page 364: ...s when in efficiency low current or performance modes UM10800 Chapter 24 LPC82x Flash controller Rev 1 2 5 October 2016 User manual Table 303 Register overview FMC base address 0x4004 0000 Name Access...

Page 365: ...be aligned on flash word boundaries i e 32 bit boundaries Once started signature generation completes independently While signature generation is in progress the flash memory cannot be accessed for o...

Page 366: ...Signature generation A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FMSSTART regis...

Page 367: ...isclaimers NXP Semiconductors N V 2016 All rights reserved User manual Rev 1 2 5 October 2016 367 of 487 NXP Semiconductors UM10800 Chapter 24 LPC82x Flash controller nextSign 31 f_Q address 31 XOR si...

Page 368: ...uration To use the IAP calls enable the IRC and the IRC output in the PDRUNCFG register see Table 54 Power configuration register PDRUNCFG address 0x4004 8238 bit description 25 4 Pin description When...

Page 369: ...1000 0x0000 13FF yes yes 5 1 80 95 0x0000 1400 0x0000 17FF yes yes 6 1 96 111 0x0000 1800 0x0000 1BFF yes yes 7 1 112 127 0x0000 1C00 0x0000 1FFF yes yes 8 1 128 143 0x0000 2000 0x0000 23FF yes yes 9...

Page 370: ...luated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request into the user accessible Flash is made writ...

Page 371: ...nd is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash CRP2 0x87654321 Access to chip via the SWD pins is disabled The...

Page 372: ...cepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID_COMMAND when an undefined command is received Commands and retu...

Page 373: ...se sector s E start sector number end sector number Table 321 Blank check sector s I start sector number end sector number Table 322 Read Part ID J Table 323 Read Boot code version K Table 325 Compare...

Page 374: ...Setting ON 1 OFF 0 Return Code CMD_SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A...

Page 375: ...te to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously Table 317 UART ISP Read Memory command Command R Input Start Address Ad...

Page 376: ...56 512 1024 SECTOR_NOT_PREPARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to program the flash memory The Prepare Sector s for Write...

Page 377: ...INVALID_SECTOR SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector s of on chip flash memory The b...

Page 378: ...Boot Code version number command Command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as byte1 Major byte0 Minor Descri...

Page 379: ...CESS followed by four 32 bit words of E sort test information in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID Table 328 UART IS...

Page 380: ...by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID_COMMAND Invalid command 2 SRC_ADDR_ERROR Source address is not on word boundary 3 DST_ADDR_ER...

Page 381: ...ON 0x1fff1ff1 Define an array or data structure to pass IAP command table and result table to the IAP function define IAP_PARAM_CT 5 define IAP_CMD_CODE 0 define IAP_PARAM_0 1 define IAP_PARAM_1 2 def...

Page 382: ...for write operation 50 decimal Table 331 Copy RAM to flash 51 decimal Table 332 Erase sector s 52 decimal Table 333 Blank check sector s 53 decimal Table 334 Read Part ID 54 decimal Table 335 Read Boo...

Page 383: ...are a single sector use the same Start and End sector numbers Table 332 IAP Copy RAM to flash command Command Copy RAM to flash Input Command code 51 decimal Param0 DST Destination flash address where...

Page 384: ...se a single sector use the same Start and End sector numbers Param2 is overwritten by the fixed value of 12 MHz which is the IRC reference clock used by the flash controller Table 334 IAP Blank check...

Page 385: ...code version number Read as byte1 Major byte0 Minor Description This command is used to read the boot code version number Table 337 IAP Compare command Command Compare Input Command code 56 decimal P...

Page 386: ...in is not accessible to force the ISP mode Table 339 IAP ReadUID command Command Compare Input Command code 58 decimal Status code CMD_SUCCESS Result Result0 The first 32 bit word at the lowest addres...

Page 387: ...25 7 1 3 UART ISP data format The data stream is in plain binary format Table 341 IAP Status codes Summary Status Code Mnemonic Description 0 CMD_SUCCESS Command is executed successfully 1 INVALID_COM...

Page 388: ...of ISP commands is located at 0x1000 0270 The maximum stack usage is 540 byte and grows downwards 25 7 2 4 RAM used by IAP command handler The maximum stack usage in the user allocated stack space is...

Page 389: ...n through simple calls to the power profile The power configuration routine configures the LPC82x for one of the following power modes Default mode corresponding to power configuration after reset CPU...

Page 390: ...umption Fig 57 Power profiles pointer structure Ptr to ROM Driver table Ptr to Device Table 2 Ptr to Device Table 1 Ptr to Device Table 1 Ptr to Device Table n set_pll set_power Power API function tab...

Page 391: ...d a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system AHB clock divider SYSAHBCLKDIV is found s...

Page 392: ...e If either of these requirements is not met set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged 26 5 1 2 Param2 mode The first priority of set_pll is to...

Page 393: ...ts characteristics The selected source can experience more or less jitter depending on the operating conditions such as power supply and or ambient temperature This is why it is suggested that when a...

Page 394: ...t0 options define PWR_CMD_SUCCESS 0 define PWR_INVALID_FREQ 1 define PWR_INVALID_MODE 2 Fig 59 Power profiles usage using power profiles and changing system clock current_clock new_clock new_mode use...

Page 395: ...hat it can provide more processing capability to the application CPU performance is 30 better than the default option PWR_EFFICIENCY setting was designed to find a balance between active current and t...

Page 396: ...et_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz The application was ready to infinitely wait for the PLL to lock Since there is no valid PL...

Page 397: ...ction 26 6 2 2 for examples of the power control API 26 6 2 1 Invalid frequency device maximum clock rate exceeded command 0 30 command 1 PWR_CPU_PERFORMANCE command 2 40 LPC_PWRD_API set_power comman...

Page 398: ...PI handles sending and receiving characters using any of the USART blocks in asynchronous mode Remark Because all USARTS share a common fractional divider the uart_init routine returns the value for t...

Page 399: ...TD_API_T end of structure define ROM_DRIVER_BASE 0x1FFF1FF8UL define LPC_UART_API UARTD_API_T ROM_API_T ROM_DRIVER_BASE pUARTD See Section 3 5 2 for how to include the ROM driver structure 27 4 1 UART...

Page 400: ...ce Table 349 uart_init Routine uart_init Prototype uint32_t uart_init UART_HANDLE_T handle UART_CONFIG set Input parameter handle The handle to the uart instance set configuration for uart operation R...

Page 401: ...uart_put_line UART_HANDLE_T handle UART_PARAM_T param Input parameter handle The handle to the uart instance param Refer to UART_PARAM_T definition Return Error code ERR_UART_SEND_ON UART sending is o...

Page 402: ...En bit2 FrameErrEn bit3 ParityErrEn bit4 RxNoiseEn 27 4 10 2 UART_HANDLE_T The handle to the instance of the UART driver Each UART has one handle so there can be several handles for up to three UART b...

Page 403: ...ter 27 LPC82x ROM API USART driver routines 0x03 For uart_get_line function RESERVED For uart_put_line function transfer is stopped after reaching 0 uint16_t driver_mode 0x00 Polling mode function is...

Page 404: ...28 3 General description The SPI API handles SPI data transfer in master and slave modes UM10800 Chapter 28 LPC82x SPI API ROM driver routines Rev 1 2 5 October 2016 User manual Fig 61 SPI driver rou...

Page 405: ...void Memory size for one SPI instance Table 357 SPI_HANDLE_T spi_setup uint32_t base_addr uint8_t ram Set up SPI instance and return handle Table 358 uint32_t spi_init SPI_HANDLE_T handle SPI_CONFIG...

Page 406: ...for SPI operation Return None Description Set up operation mode for SPI then enable SPI Table 360 spi_master_transfer Routine spi_master_transfer Prototype uint32_t spi_master_transfer SPI_HANDLE_T ha...

Page 407: ...by the transfer functions for the corresponding SPI block typedef void SPI_HANDLE_T define TYPE for SPI handle pointer 28 4 8 2 SPI_CONFIG_T Typdef struct uint32_t delay uint32_t divider uint32_t conf...

Page 408: ...egister and of several frames fsize_sel write the contents of the SPI TXCTL register to select the data length and the slave select lines In slave mode you need to only select the data length See Tabl...

Page 409: ...ode this parameter is always zero In interrupt mode error code and number of transfers will be passed to the callback In DMA mode the callback indicates the completion of the DMA transfer In master mo...

Page 410: ...clock by 0xFFFF for SCK spi_set config CFG_MASTER master mode spi_set error_en STAT_RXOVERRUN STAT_TXUNDERRUN 6 Initialize SPI transfer pSpiApi spi_init spi_handle spi_set 7 Enable the SPI interrupt i...

Page 411: ...size_in_bytes pSpiApi spi_get_mem_size size_in_bytes 4 must be RAMBLOCK_H spi_handle pSpiApi spi_setup LPC_SPI0_BASE uint8_ start_of_ram_block0 5 Set up the DMA size_in_bytes pDmaApi dma_get_mem_size...

Page 412: ...ZE size data If receive callback is invoked transmit follows automatically Only one callback is needed param callback_func_pt receive_callback DMA set up param dma_cfg dma_cfg param dma_req_func_pt dm...

Page 413: ...e tsk ch_num dma_cfg dma_txd_num tsk data_type DMA_8_BIT DMA_SRC_INC_1 memory to peripheral tsk src uint32_t driver buffer_txd tsk data_length tsk dst uint32_t lspi TXDAT tsk task_addr NULL for task h...

Page 414: ...d or receive data on the I2C bus With the I2C drivers it is easy to produce working projects using the I2C interface The ROM routines allow the user to operate the I2C interface as a Master or a Slave...

Page 415: ...driver routines i2c_isr_handler i2c_master_transmit_poll i2c_get_status Table 364 I2C API calls API call Description Reference void i2c_isr_handler I2C_HANDLE_T I2C ROM Driver interrupt service routi...

Page 416: ...intr I2C_HANDLE_T h_i2c I2C_PARAM ptp I2C_RESULT ptr ErrorCode_t i2c_slave_transmit_intr I2C_HANDLE_T h_i2c I2C_PARAM ptp I2C_RESULT ptr ErrorCode_t i2c_set_slave_addr I2C_HANDLE_T h_i2c uint32_t slav...

Page 417: ...type void i2c_isr_handler I2C_HANDLE_T Input parameter I2C_HANDLE_T Handle to the allocated SRAM area Return None Description I2C ROM Driver interrupt service routine This function must be called from...

Page 418: ..._PARAM I2C_RESULT Input parameter I2C_HANDLE_T Handle to the allocated SRAM area I2C_PARAM Pointer to the I2C PARAM struct I2C_RESULT Pointer to the I2C RESULT struct Return ErrorCode Description Firs...

Page 419: ...r Transmit Receive Interrupt Routine I2C Master Transmit Receive Interrupt Prototype ErrorCode_t i2c_master_tx_rx_intr I2C_HANDLE_T I2C_PARAM I2C_RESULT Input parameter I2C_HANDLE_T Handle to the allo...

Page 420: ...ve Receive Interrupt Routine I2C Slave Receive Interrupt Prototype ErrorCode_t i2c_slave_receive_intr I2C_HANDLE_T I2C_PARAM I2C_RESULT Input parameter I2C_HANDLE_T Handle to the allocated SRAM area I...

Page 421: ...upports four 7 bit slave addresses and masks Table 377 I2C Get Memory Size Routine I2C Get Memory Size Prototype uint32_t i2c_get_mem_size void Input parameter None Return uint32 Description Returns t...

Page 422: ...eturn Status code Description Returns status code The status code indicates the state of the I2C bus Refer to I2C Status Code Table Table 382 I2C time out value Routine I2C time out value Prototype Er...

Page 423: ...terrupts for the I2C ROM driver are used typedef void I2C_CALLBK_T uint32_t err_code uint32_t n The callback function will be called by the I2C ROM driver upon completion of a task when interrupts are...

Page 424: ...ollows typedef enum LPC_OK 0 enum value returned on Success ERROR ERR_I2C_BASE 0x00060000 0x00060001 ERR_I2C_NAK ERR_I2C_BASE 1 0x00060002 ERR_I2C_BUFFER_OVERFLOW 0x00060003 ERR_I2C_BYTE_COUNT_ERR 0x0...

Page 425: ...e i2c_get_mem_size function 2 Create the I2C handle by making a call to the i2c_setup function 3 Set the I2C operating frequency by making a call to the i2c_set_bitrate function size_in_bytes LPC_I2CD...

Page 426: ...pt driven routines non blocking Polled routines are recommended for testing purposes or very simple I2C applications These routines allow the Master to send to Slaves with 7 bit or 10 bit addresses Th...

Page 427: ...st be the slave address with the R W bit set to 1 The following conditions must be fulfilled to use the I2C driver routines in master mode For 7 bit addressing the first byte of the send buffer must h...

Page 428: ...n error Refer to the Error Code Table I2C_PARM is a structure with parameters passed to the function Section 29 4 22 I2C_RESULT is a containing the results after the function executes Section 29 4 22...

Page 429: ...ust be define Upon the completion of a read write as specified by the PARAM structure the callback functions will be invoked 29 5 6 I2C time out feature timeout Timeout time value Specifies the timeou...

Page 430: ...PI handles the calibration and set up of the ADC and allows the user to perform analog to digital conversion using the 12 bit ADC UM10800 Chapter 30 LPC82x ROM API ADC drivers Rev 1 2 5 October 2016 U...

Page 431: ...ble 385 ADC API calls API call Description Reference ADC set up uint32_t ramsize_in_bytes adc_get_mem_size void Get memory size for one ADC instance Table 386 ADC_HANDLE_T adc_setup uint32_t base_addr...

Page 432: ...ADC block ram Pointer to the memory space for ADC instance the size is obtained from adc_get_mem_size function Return The handle to corresponding ADC instance Description Sets up the ADC instance wit...

Page 433: ...b_read Prototype uint32_t adc_seqb_read ADC_HANDLE_T handle ADC_PARAM_T param Input parameter handle The handle to the ADC instance param Pointer to the ADC_PARAM_T structure Return Error code Descrip...

Page 434: ...ADC_HANDLE_T handle Input parameter handle The handle to the ADC instance Return None Description ADC interrupt service routine for overrun error interrupt When using this function the corresponding...

Page 435: ...of the system clock generated by the SYSCON block in Hz adc_clock Frequency of the ADC clock in Hz This is the clock rate for analog to digital conversions Maximum clock rate is 50 MHz for 12 bit res...

Page 436: ...in the DMA_ITRIG_INMUX register for the selected channel See Table 147 for the implemented hardware triggers and the trigger numbers The DMA transfer is configured using the DMA API After setting up...

Page 437: ...fer size is set to 32 bit Once DMA is completed only bits 4 to 15 of the buffer contain the result of the ADC conversion For non DMA mode the buffers contain the actual data from the conversion seqb_b...

Page 438: ...allback is invoked To set up the DMA channel the source address destination address and the DMA transfer length the DMA request information must be retrieved from the driver structure which is origina...

Page 439: ...bit mode disabled adc_set lpwr_mode 0 low power mode disabled adc_set thr0_low 0 threshold disabled adc_set thr0_high 0 threshold disabled adc_set thr1_low 0 threshold disabled adc_set thr1_high 0 thr...

Page 440: ...2016 All rights reserved User manual Rev 1 2 5 October 2016 440 of 487 NXP Semiconductors UM10800 Chapter 30 LPC82x ROM API ADC drivers 12 Perform conversion The result is returned in the callback fun...

Page 441: ...or debugging enable the MTB clock in the SYSAHBCLKCTRL register Table 35 Only RAM0 can be used as trace buffer by MTB that means the maximum trace buffer size is 4 KB 31 4 Pin description The SWD func...

Page 442: ...ode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset Table 398 JTAG boundary scan pin description Function Pin name Type Descri...

Page 443: ...se the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes Remark POR BOD reset or a LOW on the TRST pin puts the test TAP controller in the Test Logic Reset state The firs...

Page 444: ...uctors N V 2016 All rights reserved User manual Rev 1 2 5 October 2016 444 of 487 NXP Semiconductors UM10800 Chapter 31 LPC82x Serial Wire Debug SWD Remark The MTB BASE register is not implemented Rea...

Page 445: ...ns to overload and operators in C 32 3 General description The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 66 shows the...

Page 446: ...d denominator Unsigned integer division IDIV_RETURN_T sidivmod int numerator int denominator Signed integer division with remainder UIDIV_RETURN_T uidivmod unsigned numerator unsigned denominator Unsi...

Page 447: ...e uidiv Prototype int uidiv int32_t numerator int32_t denominator Input parameter numerator Numerator signed integer denominator Denominator signed integer Return Unsigned division result without rema...

Page 448: ...ption 32 5 1 Signed division The example C code listing below shows how to perform a signed integer division via the ROM API Divide 99 by 6 int32_t result result pROMDiv sidiv 99 6 result now contains...

Page 449: ...n be assigned to a pin Once any function is assigned to a pin the pin s GPIO functionality is disabled Pin PIO0_4 triggers a wake up from Deep power down mode If you need to wake up from Deep power do...

Page 450: ...0 In deep power down mode this pin must be pulled HIGH externally The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed and...

Page 451: ...ose port 0 input output 19 A ADC_7 ADC input 7 PIO0_20 ADC_6 29 2 I PU IO PIO0_20 General purpose port 0 input output 20 A ADC_6 ADC input 6 PIO0_21 ADC_5 28 2 I PU IO PIO0_21 General purpose port 0 i...

Page 452: ...l down resistors and configurable hysteresis 6 True open drain pin I2C bus pins compliant with the I2C bus specification for I2C standard mode I2C Fast mode and I2C Fast mode Plus Do not use this pad...

Page 453: ...unctions 34 2 Code examples I2C 34 2 1 Definitions UM10800 Chapter 34 LPC82x Code examples Rev 1 2 5 October 2016 User manual Table 405 I2C Code example I2C defines define I2C_CFG_MSTEN 0x1 define I2C...

Page 454: ...address and 1 for RWn bit in order to read data LPC_I2C MSTCTL I2C_MSTCTL_MSTSTART repeated start nack implied if mst_state I2C_STAT_MSTSTX LPC_I2C MSTCTL I2C_MSTCTL_MSTSTOP stop transaction LPC_I2C...

Page 455: ...PENDING if LPC_I2C STAT I2C_STAT_MSTSTATE I2C_STAT_MSTST_IDLE abort Table 409 I2C Code example Master write one byte to subaddress on slave Address 0x23 subaddress 0xaa Data 0xdd Polling mode No error...

Page 456: ...on while LPC_I2C STAT I2C_STAT_MSTPENDING if LPC_I2C STAT I2C_STAT_MSTSTATE I2C_STAT_MSTSTX abort LPC_I2C MSTDAT 0x23 1 1 address and 1 for RWn bit in order to write subaddress LPC_I2C MSTCTL I2C_MSTC...

Page 457: ...send data LPC_I2C MSTCTL I2C_MSTCTL_MSTCONTINUE continue transaction while LPC_I2C STAT I2C_STAT_MSTPENDING if LPC_I2C STAT I2C_STAT_MSTSTATE I2C_STAT_MSTST_NACKX abort LPC_I2C MSTCTL I2C_MSTCTL_MSTS...

Page 458: ...ss and 1 for RWn bit in order to read data LPC_I2C MSTCTL I2C_MSTCTL_MSTSTART repeated start nack implied while LPC_I2C STAT I2C_STAT_MSTPENDING LPC_I2C MSTCTL I2C_MSTCTL_MSTSTOP stop transaction whil...

Page 459: ...AT I2C_STAT_SLVSTATE I2C_STAT_SLVSTX abort LPC_I2C SLVDAT 0xdd write data LPC_I2C SLVCTL I2C_SLVCTL_SLVCONTINUE continue transaction Table 418 I2C Code example Slave read one byte from master into sub...

Page 460: ...SLVPENDING if LPC_I2C STAT I2C_STAT_SLVSTATE I2C_STAT_SLVST_ADDR abort LPC_I2C SLVCTL I2C_SLVCTL_SLVCONTINUE ack address while LPC_I2C STAT I2C_STAT_SLVPENDING if LPC_I2C STAT I2C_STAT_SLVSTATE I2C_ST...

Page 461: ...MSTIDLE 0x100 define SPI_TXDATCTL_SSEL_N s s 16 define SPI_TXDATCTL_EOT 1 20 define SPI_TXDATCTL_EOF 1 21 define SPI_TXDATCTL_RXIGNORE 1 22 define SPI_TXDATCTL_FLEN l l 24 Table 423 SPI Code example I...

Page 462: ...GNORE SPI_TXDATCTL_EOT SPI_TXDATCTL_SSEL_N 0xe 0xdd while LPC_SPI STAT SPI_STAT_MSTIDLE Table 425 SPI Code example Receive one byte from slave 0 LPC_SPI CFG SPI_CFG_MASTER SPI_CFG_ENABLE while LPC_SPI...

Page 463: ...XDATCTL SPI_TXDATCTL_FLEN 7 SPI_TXDATCTL_EOT SPI_TXDATCTL_SSEL_N 0xe 0xdd while LPC_SPI STAT SPI_STAT_RXRDY data LPC_SPI RXDAT if data 0xdd abort while LPC_SPI STAT SPI_STAT_MSTIDLE Table 428 SPI Code...

Page 464: ...TAT SPI_STAT_TXRDY LPC_SPI TXDATCTL SPI_TXDATCTL_FLEN 7 0xdd while LPC_SPI STAT SPI_STAT_RXRDY data LPC_SPI RXDAT if data 0xdddd abort while LPC_SPI STAT SPI_STAT_RXRDY data LPC_SPI RXDAT if data 0xdd...

Page 465: ..._DATALEN 8 UART_CFG_ENABLE while LPC_USART STAT UART_STAT_RXRDY data LPC_USART RXDAT if data 0xdd abort Table 436 UART Code example Transmit and receive one byte of data LPC_USART CFG UART_CFG_DATALEN...

Page 466: ...okbook 6 ARMv6 M Architecture Reference Manual UM10800 Chapter 35 Supplementary information Rev 1 2 5 October 2016 User manual Table 439 Abbreviations Acronym Description A D Analog to Digital ADC Ana...

Page 467: ...miconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunc...

Page 468: ...og oscillator control register WDTOSCCTRL address 0x4004 8024 bit description 37 Table 28 Internal resonant crystal control register IRCCTRL address 0x4004 8028 bit description 38 Table 29 System rese...

Page 469: ...PINASSIGN9 address 0x4000 C024 bit description 85 Table 77 Pin assign register 10 PINASSIGN10 address 0x4000 C028 bit description 86 Table 78 Pin assign register 11 PINASSIGN11 address 0x4000 C02C bit...

Page 470: ...scription 139 Table 133 Pin interrupt active level or falling edge interrupt set register SIENF address 0xA000 4014 bit description 140 Table 134 Pin interrupt active level or falling edge interrupt c...

Page 471: ...Receiver Data register RXDAT address 0x4006 4014 USART0 0x4006 8014 USART1 0x4006 C014 USART2 bit description 199 Table 182 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USART...

Page 472: ...ualifier 0 register SLVQUAL0 address 0x4005 0058 I2C0 0x4005 4058 I2C1 0x4007 0058 I2C2 0x4007 4058 I2C3 bit description 253 Table 220 Monitor data register MONRXDAT address 0x4005 0080 I2C0 0x4005 40...

Page 473: ...it description 316 Table 269 Global interrupt flag register IRQ_FLAG address 0x4000 40F8 bit description 316 Table 270 Register overview SysTick timer base address 0xE000 E000 318 Table 271 SysTick Ti...

Page 474: ...eration command 383 Table 332 IAP Copy RAM to flash command 383 Table 333 IAP Erase Sector s command 384 Table 334 IAP Blank check sector s command 384 Table 335 IAP Read Part Identification command 3...

Page 475: ...le 413 I2C Code example 457 Table 414 I2C Code example 458 Table 415 I2C Code example 458 Table 416 I2C Code example 458 Table 417 I2C Code example 459 Table 418 I2C Code example 459 Table 419 I2C Cod...

Page 476: ...ost_delay 223 Fig 27 Frame_delay 224 Fig 28 Transfer_delay 225 Fig 29 Examples of data stalls 228 Fig 30 I2C clocking 230 Fig 31 I2C block diagram 235 Fig 32 SCT clocking 258 Fig 33 SCT connections 25...

Page 477: ...Register 3 25 4 4 10 Interrupt Priority Register 4 25 4 4 11 Interrupt Priority Register 5 26 4 4 12 Interrupt Priority Register 6 26 4 4 13 Interrupt Priority Register 7 26 Chapter 5 LPC82x System co...

Page 478: ...modes and WWDT lock features 69 6 7 3 Active mode 69 6 7 3 1 Power configuration in Active mode 69 6 7 4 Sleep mode 69 6 7 4 1 Power configuration in Sleep mode 70 6 7 4 2 Programming Sleep mode 70 6...

Page 479: ...rs 127 9 5 7 GPIO port set registers 127 9 5 8 GPIO port clear registers 127 9 5 9 GPIO port toggle registers 128 9 5 10 GPIO port direction set registers 128 9 5 11 GPIO port direction clear register...

Page 480: ...r 175 12 6 11 Interrupt A register 176 12 6 12 Interrupt B register 176 12 6 13 Set Valid register 176 12 6 14 Set Trigger register 177 12 6 15 Abort registers 177 12 6 16 Channel configuration regist...

Page 481: ...235 15 6 1 I2C Configuration register 237 15 6 2 I2C Status register 239 15 6 3 Interrupt Enable Set and read register 243 15 6 4 Interrupt Enable Clear register 244 15 6 5 Time out value register 245...

Page 482: ...LPC82x Windowed Watchdog Timer WWDT 17 1 How to read this chapter 296 17 2 Features 296 17 3 Basic configuration 296 17 4 Pin description 297 17 5 General description 297 17 5 1 Block diagram 298 17...

Page 483: ...21 7 2 1 Avoiding spurious hardware triggers 349 21 7 3 Software triggered conversion 350 21 7 4 Interrupts 350 21 7 4 1 Conversion Complete or Sequence Complete interrupts 350 21 7 4 2 Threshold Comp...

Page 484: ...art Identification number IAP 384 25 6 2 6 Read Boot code version number IAP 385 25 6 2 7 Compare address1 address2 no of bytes IAP 385 25 6 2 8 Reinvoke ISP IAP 386 25 6 2 9 ReadUID IAP 386 25 6 2 10...

Page 485: ...I2C Master Transmit and Receive Polling 418 29 4 5 I2C Master Transmit Interrupt 418 29 4 6 I2C Master Receive Interrupt 419 29 4 7 I2C Master Transmit Receive Interrupt 419 29 4 8 I2C Slave Receive...

Page 486: ...slave 454 34 2 4 Master read one byte from slave 455 34 2 5 Master write one byte to subaddress on slave 455 34 2 6 Master read one byte from subaddress on slave 456 34 2 7 Master receiving nack on ad...

Page 487: ...Date of release 5 October 2016 Document identifier UM10800 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal infor...

Reviews:

No comments