UM10800
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
User manual
Rev. 1.2 — 5 October 2016
129 of 487
NXP Semiconductors
UM10800
Chapter 9: LPC82x General Purpose I/O (GPIO)
9.6 Functional description
9.6.1 Reading pin state
Software can read the state of all GPIO pins except those selected for analog input or
output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O
Configuration” in order to read its state. There are four ways to read pin state:
•
The state of a single pin can be read with 7 high-order zeros from a Byte Pin register.
•
The state of a single pin can be read in all bits of a byte, halfword, or word from a
Word Pin register.
•
The state of multiple pins in a port can be read as a byte, halfword, or word from a
PORT register.
•
The state of a selected subset of the pins in a port can be read from a Masked Port
(MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its
MPORT register.
9.6.2 GPIO output
Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of
write operations to the pins. Two conditions must be met in order for a pin’s output bit to
be driven onto the pin:
1. The pin must be selected for GPIO operation in the switch matrix (this is the default),
and
2. the pin must be selected for output by a 1 in its port’s DIR register.
If either or both of these conditions is (are) not met, writing to the pin has no effect.
There are multiple ways to change GPIO output bits:
•
Writing to a Byte Pin register loads the output bit from the least significant bit.
•
Writing to a Word Pin register loads the output bit with the OR of all of the bits written.
(This feature follows the definition of truth of a multi-bit value in programming
languages.)
•
Writing to a port’s PORT register loads the output bits of all the pins written to.
•
Writing to a port’s MPORT register loads the output bits of pins identified by zeros in
corresponding positions of the port’s MASK register.
•
Writing ones to a port’s SET register sets output bits.
Table 125. GPIO port direction toggle register (DIRNOT0, address 0xA000 2480) bit
description
Bit
Symbol
Description
Reset
value
Access
28:0
DIRNOTP Toggle direction bits (bit 0 = PIO0_0, bit 1 =PIO0_1, ..., bit
28 = PIO0_28).
0 = no operation.
1 = Toggle direction bit.
NA
WO
31:29 -
Reserved.
0
-