UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
962 of 1441
NXP Semiconductors
UM10503
Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)
30.6.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L and START_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
30.6.7 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L and COUNT_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation. In this case, the L and H registers count
independently under the control of the other registers.
Attempting to write a counter while it is running does not affect the counter but produces a
bus error. Software can read the counter registers at any time.
30.6.8 SCT state register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
Table 721. SCT stop condition register (STOP - address 0x4000 0010) bit description
Bit
Symbol
Description
Reset
value
15:0
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
Table 722. SCT start condition register (START - address 0x4000 0014) bit description
Bit
Symbol
Description
Reset
value
15:0
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
Table 723. SCT counter register (COUNT - address 0x4000 0040) bit description
Bit
Symbol
Description
Reset
value
15:0
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.
0
31:16
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.
0
